ECE 4263 - Introduction to VLSI Design - Spring 2012

The textbook for this course is "CMOS VLSI Design: A Circuits and Systems Perspective (4th Edition)" by Neil Weste and David Harris, Addison Wesley, ISBN: 0-321-54774-8. This same textbook will also be used in the follow-on graduate course, ECE 8273, VLSI Systems.

The class email is ece4263-01.spring2012@courses.msstate.edu . I will use this periodically to announce information about the course such as modifications to homeworks, labs, test dates, etc.

This is an upper level course, and thus is taught in a different style than what I use in a lower level course. READ THIS -- it will give you a clue as to what to expect in this class.

TBA

These lecture notes are either directly authored by David Harris, Harvey Mudd College or else is my intepretation of that material. More notes will be posted as we progress through the semester.

1. Overview of VLSI Design, Chapter 1 (1.1 to 1.5).
2. MIPS Processor example, Chapter 1 (1.6-1.12).
3. CMOS Gate Layout, Chapter 1 (1.5), Chap 3 (3.1 to 3.3).
4. MOS Transistor Theory , Chapter 2.
5. Notes on transistor sizing , Chapter 2.
6. MOS Non-ideal Transistors , Chapter 2. News item on new gate materials for lower leakage, News item on technique for improving electron mobility, IBM Link on strained silicon
7. Inverter DC and Transient response , Chapter 2.
8. Basic RC inverter delay model, improving average delay, skewed gates
9. Delay prediction using a 2D Lookup Table
11. Power Management ,Chapter 5
Interconnect (Wires) Chapter 6
12. Combinational Circuits, Chapter 9
13. Circuit Families, Chapter 9
14. DCVSL Logic, Chapter 9
15. Charge Coupling Problem, dynamic logic
16. Sequential Circuits
17. Clocking/Skew
18. Packaging, IO, Chapter 13
19. SRAMS , Chapter 12
20. Memory Decoding , Notes
21. CPU Evolution

Logical Effort Timing Model

In Spring 2012, we will not discussing the logical effort model very deeply, here are some reference notes.

1. Harris notes on Logical Effort Chapter 4
2. Sutherland notes on Logical effort
3. Tilos Gate Sizing, more notes on Logical Effort Chapter 4

Topics directly covered in lectures

The lecture notes above cover more topics than what is directly covered in lectures, you are expected to read the entire chapter to see how the rest of the chapter material relates to what is covered in class. On tests, you will be given detailed study objectives that describe what you will be tested on.

• Chapter 1: Static CMOS gate design, Pass transisors, Transmission gate, MOS transistors (1.3, 1.4)
• Chapter 1: Stick Layout, Area Estimation (1.5)
• Chapter 1: CMOS Inverter Cross Section (1.5.1), CMOS Fabrication (1.5.2), MOS operation (Figure 2.3)
• Silicon Run DVD - covers fabrication steps (read Chapter 3 for a deeper understanding)
• Datapath design style (Fig 10.5(b)) vs. Standard Cell layout (Fig 10.5a, Figure 1.62)
• MOS Transistor theory, Section 2.1, 2.2
• MOS Non-ideal Effects, Section 2.4.
• Design Corners 4.7.1-thru 4.7.4
• C-V Characteristics, 2.3
• RC Delay Model, linear delay model, Section 4.2
• Theory of Logical Effort, Section 4.3
• Interconnect, Wire Engineering, Sections 4.5, 4.6

This is a preliminary test schedule, tests are closed textbook, closed notes, four-function or scientific calculator only.

• Test #1, February 14, Test 1 Study Guide
• Test #2, March 8, Test 2 Study Guide
• Test #3, April 17, Test 3 Study Guide , Test #3 Solution

Some of these lab exercises (the Java Electric labs) were originally authored by David Harris and have been modified for use at MSU. You are expected to attend the lab period and work on the lab exercise until you have completed it. This is so that I get a warm and fuzzy feeling that you are progressing on the lab, and also so that if I answer a question for one student, the rest of you can hear it. You can work on the lab exercises anytime that you wish; and in fact, most labs will also require work outside of the lab period. I will count attendance at a lab session in the same way as attendance in the lecture for the extra points assigned to the test pool.

If you have not submitted a lab by the time I am ready to grade it, I reserve the right to reject the lab.

Lab submissions are due at the beginning of the lab period of the week that they are due. I grade the labs during the first part of the lab period. If the lab is not submitted by the time I am ready to grade it during the lab period, it will be given a '0' grade. When grading your lab, if I have a question about your lab that will affect its grade, and you are not there to answer my question, then I will simply give the lab grade a 0. Students are supposed to attend the lab session to work on the next lab so that I will be available if you have questions, and also if I have questions about your lab submission. The later labs require some of the components created in the earlier lab, so you will need to complete layout work required in a lab in order to complete later labs, even if you have to complete it after the submission date. KEEP BACKUP COPIES of all of your lab files, especially the library files created by Electric.

• Jan 9 - no required lab meeting.
• Jan 16 - Lab#1, Intro, Week due: Jan 23 (just the NAND2 schematic and IRSIM simulation). Jan 16th is a HOLIDAY, so Monday lab students will be one week behind the Wednesday lab students.
  Files (right click and save to disk)
  • mipsparts.elib , UPDATED ON JAN 7/2010.
  • Submission script, parta , expects files lab1_intro/lab1.elib, lab1_intro/and2.cmd.
  • vlsi_lab1_schem.wmv, Video tutorial on Electric schematic capture.
• Jan 23 - Lab#1, Week due: Jan 30 (Lab1, finish part A ).
  Files (right click and save to disk)
  • Submission script, parta , expects files lab1a/lab1.elib, lab1a/and2.cmd.
  • vlsi_lab1_layout.wmv, Video tutorial on layout using Electric, part 1. Shows first part of NAND2 layout.
  • vlsi_lab1_layout2.wmv, Video tutorial on layout using Electric, part 2. Shows second part of NAND2 layout.
  • vlsi_lab1_and2.wmv, Video tutorial on heirarchical layout using Electric. Shows AND2 layout assignment of lab1.
• Jan 30 - Lab#1:part B (use same lab writeup), Week due: Feb 6.
  Lab1 Files (right click and save to disk)
  • Submission script, partb
  , expects files lab1b/lab1.elib, lab1b/or2.cmd.
• Feb 6 - Lab#2 , Week due: Feb 13
  Lab2 Files (right click and save to disk)
  • fulladder.cmd
  • Submission script, expects files lab2/lab2.elib, lab2/fulladder.cmd.
• Feb 13 - Lab#3, Week due: Feb 20 (Lab3, part A).
  Files (right click and save to disk)
  • alu.cmd
  • Submission script, part A, expects files lab3a/lab3.elib, lab3a/report.pdf.
• Feb 20 - Lab#3, part B (use same lab writeup), Week due: Feb 27.
  Files (right click and save to disk)
  • Submission script, part B, expects files lab3b/lab3.elib, lab3b/report.pdf.
• Feb 27 - Lab#4 - Spectre Simulation Introduction , Week due: Mar 5
  This lab introduces the use of Cadence Spectre for simulation. For additional documentation on Spectre, click here to explore the documentation (the document 'spectreuser.pdf' is the best overview of Spectre for new users). Also please read the instructions in the tools section about installing Xwin32 on your system for X-windows display if you are running Windows. You will need this to display GUI windows from the Spectre Waveform tool on your PC. When you create your directory for your submission script, please delete any of .raw spectre output directories as these can be quite large.
  Files (right click and save to disk)
  • Submission script, Expects files 'lab4/report.pdf', 'lab4/spreadsheet.xls'
  • ZIP archive of Spectre files
  • Spreadsheet containing data tables for report
• Mar 5 - Lab#5: Gate Sizing, Transistor Sizing , Week due: Mar 19
  
  Files (right click and save to disk)
  • Submission script, Explicitly checks for 'lab5/report.pdf', 'lab5/sizing_template.xls'
  • ZIP archive of Spectre files
• Mar 12 - Spring Break
• Mar 19 - Lab#6, Week due: Mar 26 (Lab6, part A).
  Files (right click and save to disk)
  • ZIP archive
  • Submission script, part A,expects files lab6a/results.xls, lab6a/report.pdf.
• Mar 26 - Lab#6, part B (use same lab writeup), Week due: Apr 2.
  Files (right click and save to disk)
  • Submission script, part B,expects files lab6b/report.pdf.
• Apr 2 - Lab#7 - Standard Cell Place/Route Due Date for all sections: Apr 9. WARNING: The grade for this lab is based mostly on the LAB REPORT, as the reporting requirements are extensive for this lab.
  
Files (right click and save to disk)
• Submission script, Explicitly checks for 'lab7/lab7.jelib', 'lab7/report.pdf', 'lab7/alucontrol.def', 'lab7/controller.def'
• ZIP archive
• LEF/DEF File Format , (can only access if logged into MSU ECE network)
• Apr 9 - Lab#8 - Chip Assembly Due Date for all sections: Friday, April 25th
  
  
Files (right click and save to disk)
• Submission script, Explicitly checks for 'lab8/report.pdf', 'lab8/alucontrol.def', 'lab8/controller.def', 'lab8/lab8.jelib
• ZIP archive

Other labs to be announced.

Lab Submissions

Each lab has a submission perl script, a typical name is 'submit_lab1.pl'. The submission script is used to mail your lab files to the instructor. Each lab writeup has a list of files that need to be submitted. On yavin, create a directory named 'labn', (i.e., lab1 or whatever the script expects)), and place all of the files to be submitted in that directory. Copy the perl script to the directory above that directory. Log into to yavin.ece.msstate.edu, and change to the directory that contains the perl script and the 'labn' subdirectory. Execute the perlscript via the command 'perl scriptname, i.e. 'perl submit_lab1.pl'. This will pack up the submission directory and mail it to both yourself and the instructor (verify that you have received a copy of the submission, else resubmit!!!!). You will not be able to read the attachment, just verify that you got something. You can submit multiple times, only the latest submission will be used. For the majority of the labs, the reporting requirements are minimal; generally I will be looking for something tangible such as a VLSI layout or simulation result.

If you are confused about how to log into yavin.ece.msstate.edu or how to place your files on the ECE disk space, please see the ECE Computer Help Desk . You will need to be able to upload files to your directory space on yavin, so look around for a good FTP client.

Lab Grading

Labs will be graded on an 'A' (100), 'B' (85), 'C' (75), 'D' (65) or 'F' (0) basis. No other grades will be assigned for a lab assignment. An 'A' grade will be assigned if the lab submission meets all of the requirements. The other grades are assigned based on how well the lab fulfills the lab requirements.

Late Lab Policy

A lab is late is not turned in by the beginning of the lab period when it is due. I reserve the right to reject any late lab with a grade of 0. If for some reason I accept a late lab, and it will be on a case by case basis, and I will reserve the right to only assigned a grade of 'C', 'D', or 'F'. Any lab more than one calendar week late late will be assigned a grade of 'F'.

Homeworks are due at the beginning of the class period at the date shown. For the layout stick diagrams, you will need need colored pens or pencils with the following colors: red, blue, green, yellow, black.

• Jan 17: Chapter 1 (1.5, 1.6a, 1.6b, 1.9b). For problem 1.9b, this must done in one logic level since you have dual rail inputs. You will need to use DeMorgan's theorem to transform this into a boolean equation with an inverted output.
• Jan 24: Chapter 1 (1.10, 1.16a,b,c, 1.18a,b,c 1.19). In your stick diagrams account for metal1 contacts to all inputs . Here is some Stick Diagram grid paper . Also, if your input has to be connected to multiple transistors, you have to do this within your stick diagram. You can only use Metal 1 and Poly for interconnect, you cannot use Metal 2. The layouts can be done with unbroken diffusion, but may require poly routing of gate connections if an input goes to more than one transistor of the same type.
• Jan 31: Chapter 3 Homework
• Feb 7: Chapter 2 Homework
• Feb 22: Chapter 4 homework, Elmore Delay
• Feb 21: RC Delay Model, Spreadsheet
• Mar 1: 2D Delay Model Homework, Spreadsheet
• Mar 27: Chapters 5,6 homework
• Apr 3: Chapter 9,10 homework
• Apr 10: SRAM,IO homework

Other homeworks to be announced.

VLSI design is tool intensive; we will be using the following design tools:

• Java Electric, a Java-based layout tool. We are using a modified version from what is available on the web, you must be logged on to the MSU ECE network to download the tool.
  • Click here first to log in, then navigate back.
  • You should be using some version of Java 6 ( Java 6.x, aka 1.6.x) . Download electric-8.05e_java6.jar for use with Java 6.x.
• Cadence Spectre (a blend of SPICE and Verilog-A), this runs on the Linux machines in the department, which you log into remotely and then display an X-window back on your local machine. We will be using this later in the semester; you will need to install X-WIN32 on your PC (the University has a site license for this, see the MsState Information Technology Services website for information on downloading this client. When you download this, be sure to choose the SSH version of XWIN32, also copy the license key (a long text string) that pops up in the browser during the ITS download and save this to a text file. Once XWIN32 is installed, when you run it an icon will appear in your tray. To save the license, right click on this icon, choose "Support>Licenses", click "Add", and paste the license into the box.
• If you are having trouble getting X-windows forwarded to your PC, this document has some screenshots of putty being configured to allow X11 forwarding. Student have had trouble getting X11 forwarding to work unless they have a hardwired connection to ECE. If you do use a wireless connection, be sure to use the VPN.
• Synopsys Design Compiler (logic synthesis) and JupiterXT (chip construction, floorplanning, standard cell place/route). We will use these later in the semester, these tools run on the Linux machines in the department, which you log into remotely and then display an X-window back on your local machine.

We have moved to Java Electric System for the front-end layout system instead of using Cadence. This is because the complexity of the layouts that we are doing is such that these layouts can be created in Electric just fine on your PC, and you can work on your VLSI layouts at home outside of lab while munching popcorn and watching a movie. Manual layout can be tedious, and it can require a considerable amount of time to become comfortable with any layout tool, and having to be connected to the MSU network to run Cadence can be a barrier to spending the time needed to become comfortable with the tool. The concepts you learn in Java Electric will easily transfer to a commercial layout tool such as Cadence; it is simply a different GUI. We will use commercial tools such as Synopsys for larger automated layouts later in the semester.

Griping about VLSI Tools

It is a fact that ECAD tools of any type will screw up and cause you personal grief. As such, it is your GOD-GIVEN RIGHT to gripe about the tools! Feel free to gripe all you want - things that might make you feel better after a frustrating hour or two:

• Scribble things on your Facebook wall! Let everybody know how miserable you are! Scribble things on MY facebook wall and let me know what a great time you are having!
• Stand on the sidewalk outside of Simrall and mumble incoherently, loudly. Do this between classes so that others get maximum exposure to your mumbling. Watching the reactions of others to your incoherent rants will make you feel better, guaranteed.
• Create a website dedicated to your griping, like 'I_Hate_VLSI_TOOLS.info', make it a wiki, and invite students from across the nation to join you in your griping!
• ...and there are lots more....

• Static Freesoft, Electric VLSI Design System
• Intel 32nm Technology
• Intel FINFET Technology
• Intel Trigate overview
, Intel Trigate layout
• Intel Core-i7 Second Generation
• Intel Tick-Tock Model