EE4743/6743 Digital Systems Design (Fall 2007)

Class Time & Location

MW(F) 10:00-10:50am,  Simrall 203

Instructor

Lab Instructor

Class E-mail

Textbook

R. Reese and M. Thornton, Introduction to Logic Synthesis Using Verilog HDL, Morgan & Claypool Publishers, 2006.

Grade Determination

Grading Scheme

Attendance

Students are expected to be present for all tests and for the final exam. In extreme cases, I may arrange a make-up test. I will not be taking regular attendance, but I strongly suggest coming to class as the tests are based off of material discussed in class. It is the student's responsibility to contact me in advance to explain the situation and arrange an alternate plan.

Prerequisites

1. Topics
2. Sample Exercises

In-Class Slides

0. Aug 20, 2007 (M) : Introduction
1. Aug 22, 2007 (W):  Review of combinational logic
2. Aug 23, 2007 (F):   Review of sequential logic
3. Aug 27, 2007 (M):  Review of finite state machines
4. Aug 29, 2007 (W):  Combinational Verilog
5. Aug 31, 2007 (F):   Implementation technology
6. Sept 5, 2007 (W):   Fixed point Arithmetic (Shift-add-3 algorithm)
7. Sept 7, 2007  (F):    Sequential Verilog 
8. Sept 10, 2007 (M):  Finite state machines design 
9. Sept 12, 2007 (W):  Datapath design
10. Sept 17, 2007 (M):  System Timing
11. Sept 19, 2007 (W):  Increasing the Clock Rate
12. Sept 26, 2007 (W):  Structural Verilog (VGA Graphics)
13. Sept 28, 2007 (F):   Scheduling 
14. Oct 3, 2007 (W):     Scheduling Examples
15. Oct 8, 2007 (M):     Increasing the initiation rate
16. Oct 10, 2007(W):    Linear Feedback Shift Registers (LFSR)
17. Oct 15, 2007(M):    System-on-a-Chip design
18. Oct 17, 2007(W):    Pipelining 
19. Oct 24, 2007(W):    Pulse Width Modulation
20. Oct 29, 2007(M):    IO Technology
21. Oct 31, 2007(W):    Introduction to design for Test
22. Nov 7, 2007 (W):    Introduction to design for Test
23. Nov14, 2007 (W):   Introduction to VHDL
24. Nov 28, 2007 (W):  Review for the final
    

Tests

• No calculators/PDAs/laptops/phones etc.
• Write legibly
• Make your final answers clear
• Test 1 will be a take home exam
• For Test 2-5 are closed book, closed notes.

Test 2:  Friday, September  14, 2007.

Test 3:  Friday, October 5, 2007.

Test 4:  Monday, October 22, 2007.

Test 5:  Monday, November 12, 2007.

Final Test" Friday, December 7, 2007.

Handouts 

Software

Hardware

The labs this semester will require each student to purchase the Digilent, Inc. Basys development board. These cost $59 each and can be purchased directly from the Digilent, Inc. homepage. Included with each kit is a power supply and download cable. We decided to do this so each student can have hands-on experience with FPGA hardware. Each board has 8 LEDs, 8 switches, 4 push buttons, and a 4 digit numerical display. There are also connections for a VGA monitor and a PS/2 port for keyboards/mice. We will be using all of these in the lab.

1. Basys reference manual
2. Basys board schematic

We strongly recommend doing the labs on your laptops. If your laptops do not have a parallel port, then you won't be able to use the download cable. If you don't have a suitable laptop, some computers will be available in lab for development and programming.

Labs

The labs offered this semester will have different accomplishment levels. This is designed so each student can decide how many hours he/she wants to put into the lab. Each level carries a grade of A,B,C. The labs are designed so that completing the 'C' level work will lead directly into the 'B' level work, which will in turn lead into the 'A' level work. Graduate students must complete at least the 'B' level work. There are weekly quizzes at the beginning of the lab period and a lab final during the last week of class. Be sure to bring your laptops to lab. If you do not have a laptop, then there are a few workstations that you can use.

If you use the Basys board, use the constraints file provided here. When you open the project in the lab files provided below you will have to change the FPGA for which it is synthesizing the design. Do this by right clicking on "xc3s200-4ft256" in the Sources window and select "Properties...". Change the Family to Spartan 3E, change the Device to XC3S100E, and change the Package to VQ100.

1. Week of August 27:     Lab1: Software Installation and Tutorial 
2. Week of Sept. 5:         Lab2: Combinational Verilog
3. Week of Sept 10:        Lab3: Sequential Verilog: Board Evaluation
4. Week of Sept 17:        Lab4: Finite State Machines: Calculator
5. Week of Sept 24:        Lab5: IP Cores: Pong
6. Week of Oct 1:           Lab 6: Memories:  Raster vs. Tiles 
7. Week of Oct 8:           Lab7: Image Processing: Dithering 
8. Week of Oct 15:         LFSRs: Cryptology
9. Week of Oct 22:         Pulse Width Modulation
10. Week of Oct 29:         Embedded Processors: Picoblaze
11. Nov. 14:                     Lab Final
    

• General:
  • Be sure to include the constraints file in your project. If you're seeing strange things on the outputs, this may be the problem.
  • If your code compiles, but doesn't do what you want it to: READ THE WARNINGS
    • The warnings are there to tell you that you probably made a mistake, but it will compile your code anyway
    • If it optimized something out, it will give you a warning - that's usually a mistake
    • It will tell you when it finds an asynchronous loop
    • It will tell you of unassigned I/O
• Verilog code:
  • Make simple always blocks
    • Only assign few related outputs
    • More smaller process statements are better than one big one
    • The compiler is not very smart
  • Always be able to draw a block diagram of the circuit you are trying to describe
  • Watch out for asynchronous loops in your code
    • Make sure you can't trace a combinational path
    • Temporary signals make this deceptive
• Schematic Entry:
  • Use the wire naming tool - don't double click on a wire to name it
  • If you rename a wire, it will rename all of the wires of the same name

Project

Phase 1 Due: Nov 2

Phase 2 Due: Nov 9

Phase 3 Due: Nov 16

Phase 4 Due: Nov 26

Demonstrations Nov 29 and Nov. 30 3:00-5:00 at SDS lab

4743 Project Template Page

Current Projects

• Team 1: Venkata Nookala, Lakshmi Pragada, Venkata Puvadi
• Team 2: Frank Holland  
• Team 3: Chris Dailey, Michael Weir
• Team 4: Charlie Mraz
• Team 5: Steven Austin, Jerome Walker
• Team 6: Andrew Thigpen, Joshua Wilson

Previous Projects

• Team 1: Etch-A-Sketch
• Team 2: Kaboom
• Team 3: Breakout
• Team 4: SSI System
• Team 5: Collision Warning System

Fall 2006

• Team 1: USB Robot
• Team 2: Team MCR
• Team 3: Pacman
• Team 4: Sound Recorder
• Team 5:Motion Detector
• Team 6: FPGA cluster

Spring 2006

• Team Elves: IP Cores Lab: The Baloon Hunt
• Team PWM_Audiophiles: PWM Audio Player
• Team XYZZY: FSM Lab: Maze
• Team Wireless Pong: Wireless Pong

Fall 2005

• Team Syzygy: Computer Fan Control
• Team Illumination Science: Light-Bright Toy
• Team Snooze: Alarm Clock
• Team NTN Design: PoV Game
• Team Cyclotech: Cyclocomputer

Spring 2005

• Team Ramrod: Weather Station
• Team 2: Pegasus Clock
• Team CCA: CCA Tank Monitor
• Team High Fidelity: Graphical Equalizer
• Team H.A.L.: Sunlight Replicator

Reference Material

Web pages of interest

• Verilog
• Verilog HDL Quick Reference Guide
• Introduction to Verilog
• Verilog.org
• Verilog style papers
  
• ASM web page references
• Concordia University part1, part2
• Bypass Capacitors
  • Bypass Capacitors Application Note
  • Basics - from the Seattle Robotics Society
  • Basics - from Signal Consulting Inc.
  • Placement - from InterfaceBus.com
  • Package Differences - from Mercury Computer Systems
• Transmission Lines
  • Transmission Line Basics
  • Transmission Lines - Characteristic Impedance
  • Transmission Lines - Termination Schemes
  • Reflection Calculator
• Wishbone Specifications Rev B.3
• Gameboy/Xilinx Robots
• Lego logic gates
• Nintendo DS passthrough using Digilent Spartan3 board
• Other Universities using FPGAs
  Digilent Pegasus boards
  • Universidade Federal de Santa Catarina - UFSC (Brazil)
  • Yale
  • Oregon Institute of Technology
  • University of California, Santa Cruz
  • Western Michigan University
  • Other Digilent boards
    National University of Ireland
    University of New Brunswick, Canada
    Worcester Polytechnic Institute
    • LaFayette College

Data Sheets

• PicoBlaze Processor
• Altera Stratix FPGA
• Altera Flex10K FPGA
• Altera Max 7000A FPGA
• Xilinx Virtex FPGA
• Xilinx Spartan-II FPGA
• Spartan-3 FPGA
  • Block RAM note
• Actel MXDS FPGA
• Cypress Ultra37000 CPLD
• Cypress PAL20 PLD
• Cypress PAL22V10 PLD
• Texas Instruments Logic Selection Guide: list/discussion all of the low voltage IO families

Sample Tests

• Test 4, Spring 2006
• Test 3, Spring 2006
• Test 2, Spring 2006
• Test 4, Fall 2005
• Test 3, Fall 2005
• Test 2, Fall 2005
• Test 4, Spring 2005
• Test 3, Spring 2005
• Test 2, Spring 2005
• Test 4, Fall 2004
• Test 3, Fall 2004
• Test 2, Fall 2004
• Test 3, Spring 2004
• Test 2, Spring 2004
• Test 1, Spring 2004
• Test 3, Fall 2003
• Test 2, Fall 2003
• Test 1, Fall 2003
• Test 3, Spring 2003
• Test 2, Spring 2003
• Test 1, Spring 2003
• Test 3, Fall 2002
• Test 2, Fall 2002
• Test 1, Fall 2002
• Test 2, Spring 2002
• Test 3, Spring 2000
• Test 1, Spring 2000
• Test 3, Fall 1999
• Test 2, Fall 1999
• Test 1, Fall 1999
• Test 2, Spring 1999
• Test 1, Spring 1999
• Test 2, Fall 1998
• Test 1, Fall 1998
• Test 2, Spring 1998
• Test 1, Spring 1998

Homework problems

• Homework Set 1 - Solutions
• Homework Set 2 - Solutions
• Homework Set 3 - Solutions
• Homework Set 4 - Solutions