ECE 4743/6743

COMPUTER AIDED DESIGN OF DIGITAL SYSTEMS

CATALOG DATA: ECE 4743/6743. Digital System Design. (3)

(Prerequisites: Grade of C or better in ECE 3724/CSE 3124. Credit or Registration in ECE 3243).

Two hours lecture. Three hours laboratory. Hierarchical digital design using available design software. Computer aided design workstations will be used to give students access to state-of-the-art design techniques.

PREREQUISITES BY TOPIC:

1. Computer Programming.
2. Digital Devices.

TEXTBOOK(S) AND OTHER REQUIRED MATERIAL:

1. M. Zwolinski, Digital Systems Design with VHDL, Prentice Hall, 2000.

GENERAL COURSE OBJECTIVES AND RELATIONSHIP TO PROGRAM OBJECTIVES:

1. Show students how to do computer-aided digital design. [1,2,3]
2. Develop student skills in using hardware description languages. [1,2,4]
3. Develop the students' ability to design finite state machines. [1,2]
4. Introduce students to datapath design and ASM-based controller design. [1,2]
5. Develop students' knowledge of timing analysis, clock cycle time, and design to meet timing objectives. [1,2]
6. Introduce students to contemporary design topics including professional ethics. [1,2,4]

COURSE TOPICS COVERED:

1. Implementation Technologies
2. VHDL for Combinational Logic
3. VHDL for Sequential Logic
4. VHDL for Finite State Machines.
5. Datapath Design
6. Fixed-point Arithmetic
7. Hard/Soft/Firm cores & System-on-Chip Design
8. Specific vendor FPGA architectures
9. Parameterized modules
10. Pipelining and timing Analysis
11. Board-level Design & I/O Technology
12. Resource estimation
13. Resource scheduling
14. Digital Testing
15. Other Design Topics
16. Tests (3 classes)

LABORATORY TOPICS COVERED:

1. Xilinx CAD Software & Schematic Capture
2. Combinational and Sequential VHDL Synthesis
3. Datapath/controller architectures
4. Using 3^rd-party IP Cores in system design
5. Memory management and busses
6. Resource scheduling including pipelining combinational logic
7. Timing analyzer
8. Linear Feedback Shift Registers
9. Microcode controllers
10. Moderate sized circuit for project

CONTRIBUTIONS TO PROFESSIONAL COMPONENT:

1. Engineering Science : 0.5 hours
2. Engineering Design : 2.5 hours
3. Basic Math and Science : 0 hours

ASSESSMENT:

1. Tests.
2. Final Exam.
3. Laboratory reports.
4. Final project report.

SPECIFIC COURSE OBJECTIVES AND RELATIONSHIP TO MEASURABLE OUTCOMES:

Objective 1:

• Demonstrate the ability to enter digital logic into a schematic capture package. (2,4,5,9)
• Demonstrate the ability to perform functional simulation on a digital design. (2,4,5,9)
• Demonstrate the ability to run static-path timing analysis on a design. (2,4,5,9)
• Demonstrate the ability to combine knowledge from this class in order to design a large, complex, complete system and demonstrate it in hardware. (1,2,3,4,5,6,7,9)

Objective 2:

• Demonstrate proficiency in VHDL, including both combinational and sequential logic. (2,4,5,9)

Objective 3:

• Demonstrate designs of FSM's in VHDL. (2,4,5,9)

Objective 4:

• Demonstrate the ability to convert an equation into a flowgraph. (1)
• Demonstrate proficiency in flowgraph manipulation including pipelining. (1)
• Demonstrate the ability to implement flowgraphs in hardware. (2,4,5,7,9)

Objective 5:

• Demonstrate the ability to compute clock-cycle time. (1)
• Demonstrate the ability to design interface logic between functional units using timing diagrams and specifications. (2,4,5,7,9)

Objective 6:

• Demonstrate knowledge of ethical behavior. (4,6,8)
• Demonstrate knowledge of contemporary design issues. (4,6,8)

PREPARED BY:

Dr. Justin Davis, Assistant Professor of Electrical and Computer Engineering, September 15, 2004.