From sm655 at msstate.edu Mon Nov 7 21:15:39 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Mon Nov 7 21:15:53 2011 Subject: [ece3714] Lab 9 Updated & Prelab 9 posted Message-ID: <4EB89EDB.4080304@msstate.edu> Hello, Please note that Lab 9 manual and report is updated. Also, prelab 9 quiz is posted. The due for the quiz is tomorrow midnight as usual. The questions are straightforward. It only check the basic concept of register. Just make sure you read manual before take the quiz. If you have any question, please let me know. Thank you, Sungkwang From sm655 at msstate.edu Tue Nov 15 03:35:41 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Tue Nov 15 03:35:57 2011 Subject: [ece3714] Lab 10 updated & Prelab Message-ID: <4EC2326D.4070101@msstate.edu> Hello, Lab 10 manual and report are updated. Please read and prepare for our last lab. This lab requires to read textbook in order to understand some materials including finite state machine. For prelab, please finish two problems listed in lab report using the manual and textbook. First one is drawing a state diagram, and second one is modifying DFF_clr code a little. If you have any question, please let me know. Thank you, Sungkwang From sm655 at msstate.edu Tue Nov 15 19:42:31 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Tue Nov 15 19:42:47 2011 Subject: [ece3714] Re: Prelab for lab 10 In-Reply-To: <535E6B30-7CEE-46D6-9573-873612A3C618@msstate.edu> References: <535E6B30-7CEE-46D6-9573-873612A3C618@msstate.edu> Message-ID: <4EC31507.4050603@msstate.edu> For the pralab, draw the same state diagram on figure 3.57 in the textbook. Only work you need to do is replacing the names of signals. For example, use 'start' signal instead of 's' or 'button' instead of 'button'. Also, replace the standard operator to Verilog operator, AB => A&B or A+B => A|B. It will be convenient when you write the Verilog code in the controller file. I hope you learn how to make a state diagram based on the information how the system behave. After having done the state diagram, complete the Verilog code in the lab manual. There is a example how to make equation out of the state diagram. Please read textbook and lab manual, and try to complete the given code in the manual. If you have any trouble, please let me know. We are going to learn how to verify the controller during the lab hour. Prelab will be graded before the lab starts on Wednesday. Thank you, Sungkwang On 11/15/11 PM 05:04, Chance wrote: > I am still a bit confused about what or how we are to do our schematic of the state machine. I was wondering if you might could explain a little more. Thanks > From sm655 at msstate.edu Wed Nov 16 09:17:55 2011 From: sm655 at msstate.edu (SungKwang Mun) Date: Wed Nov 16 09:18:06 2011 Subject: [ece3714-01] [ece3714] Re: Prelab for lab 10 In-Reply-To: References: <535E6B30-7CEE-46D6-9573-873612A3C618@msstate.edu> <4EC31507.4050603@msstate.edu> Message-ID: <4EC3D423.8050900@msstate.edu> Perry, That's a part of the prelab. We will have some time to verify the results using waveform. It will be very helpful if you try first. In the presentation today, we will answer the questions you might have during the programming. If you start it during lab, that will take much more time. I will forward this to the students in our lab. Sungkwnag Perry Clark wrote: > Hi, > > What do you mean when you say "Complete the Verilog Code?" Is the part > of the prelab or are you suggesting we start the lab ahead of time? > > Perry Clark > > On Tue, Nov 15, 2011 at 7:42 PM, Sungkwang Mun > wrote: > > > For the pralab, draw the same state diagram on figure 3.57 in the > textbook. Only work you need to do is replacing the names of > signals. For example, use 'start' signal instead of 's' or > 'button' instead of 'button'. Also, replace the standard operator > to Verilog operator, AB => A&B or A+B => A|B. It will be > convenient when you write the Verilog code in the controller file. > I hope you learn how to make a state diagram based on the > information how the system behave. > > After having done the state diagram, complete the Verilog code in > the lab manual. There is a example how to make equation out of the > state diagram. Please read textbook and lab manual, and try to > complete the given code in the manual. If you have any trouble, > please let me know. We are going to learn how to verify the > controller during the lab hour. > > Prelab will be graded before the lab starts on Wednesday. > > Thank you, > > Sungkwang > > On 11/15/11 PM 05:04, Chance wrote: > > I am still a bit confused about what or how we are to do our > schematic of the state machine. I was wondering if you might > could explain a little more. Thanks > > _______________________________________________ > ece3714 mailing list > ece3714@ece.msstate.edu > http://www.ece.msstate.edu/mailman/listinfo/ece3714 > _______________________________________________ > ece3714-01 mailing list > ece3714-01@ece.msstate.edu > http://www.ece.msstate.edu/mailman/listinfo/ece3714-01 > > From sm655 at msstate.edu Wed Nov 16 11:13:02 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Wed Nov 16 11:13:17 2011 Subject: [ece3714] Some detail on implementation Message-ID: <4EC3EF1E.8010501@msstate.edu> Hello, I tried to make a bit clear on implementation part of our project today. If you read the lab manual, you might know that there is a two parts in the sequential circuit (or controller in our lab), which are combinational circuit and memory (D flipflop in our lab). Combinational circuit determines which state to proceed from current state. Memory keeps the data in a single clock period and feed back to the input (current state) of the combinational circuit. First image attached here is the same diagram in the lab manual. We are trying to capture the transition for the START state using incoming conditions indicated orange arrows. There are two conditions(~button, start) and two states(WAIT, START) that originate the conditions. In order to determine the NEXT STATE, each condition has to be considered with the condition which originate. Each arrow can be treated as option which means one of conditions(one of the arrows) makes the transition to the START state. Here are the Verilog code and the circuit diagram. First two lines defines the state which originate the condition of the transition. Third line is defines the next transition using the state information and the condition of the transition. Because one condition is enough to make a transition, we use OR operation on both of the condition. DFF is followed to store the information for a single clock and pass the information to the input of the combinational circuit. I hope this would be helpful for you to write other codes in controller. assign WAIT_S = ~STATE[5]&~STATE[4]&~STATE[3]&~STATE[2]&~STATE[1]& STATE[0]; assign START_S = ~STATE[5]&~STATE[4]&~STATE[3]&~STATE[2]& STATE[1]&~STATE[0]; assign NEXT_STATE[1] = (WAIT_S&START)|(START_S&~BUTTON); DFF_clr D1(CLK, ACLR, NEXT_STATE[1], STATE[1]); See you in the lab. Sungkwang -------------- next part -------------- A non-text attachment was scrubbed... Name: capture_01.jpg Type: image/jpeg Size: 30593 bytes Desc: not available Url : http://www.ece.msstate.edu/pipermail/ece3714/attachments/20111116/513944ca/capture_01-0001.jpg -------------- next part -------------- A non-text attachment was scrubbed... Name: wait_state.png Type: image/png Size: 17702 bytes Desc: not available Url : http://www.ece.msstate.edu/pipermail/ece3714/attachments/20111116/513944ca/wait_state-0001.png From sm655 at msstate.edu Thu Nov 17 15:33:07 2011 From: sm655 at msstate.edu (SungKwang Mun) Date: Thu Nov 17 15:33:19 2011 Subject: [ece3714] Re: Lab10 report In-Reply-To: <6053FA99-91DB-407C-8726-0B6BA41D3E98@msstate.edu> References: <6053FA99-91DB-407C-8726-0B6BA41D3E98@msstate.edu> Message-ID: <4EC57D93.1060107@msstate.edu> Chance, The lead is just current state information after the single clock. Exclusiveness of the one-hot encoding makes it possible to have 1 bit state information instead of 6bit state information. For example, NEXT_STATE[1] is START state according to the encoding table, the current state, STATE[1], becomes START state after one clock cycle. The purpose of the DFF is memory to keep the previous value for deciding next transition to other states. That's why it has feedback lead to the input of the combinational logic. If you take a look at previous email 'some detail on implementation' might give you better understanding. I will forward this to the students in our lab. Thanks, Sungkwang Chance wrote: > Hey this is Chance Sistrunk, ces338, from digital devices lab. I am working on my schematic and was wondering why you had your feedback out of Q tied to the particular leads you have and how you knew to tie them there. Any help is appreciated. Thank you. > > Sent from my iPhone From sm655 at msstate.edu Mon Nov 21 14:01:22 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Mon Nov 21 14:01:35 2011 Subject: [ece3714] *Important* Practicum (Final Lab Test) Schedule Message-ID: <4ECAAE12.5060008@msstate.edu> Skipped content of type multipart/alternative-------------- next part -------------- A non-text attachment was scrubbed... Name: FinalExamForLab.xlsx Type: application/octet-stream Size: 10841 bytes Desc: not available Url : http://www.ece.msstate.edu/pipermail/ece3714/attachments/20111121/b77bbc47/FinalExamForLab.obj From sm655 at msstate.edu Mon Nov 21 14:03:54 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Mon Nov 21 14:04:00 2011 Subject: [ece3714] Lab 10 report due Message-ID: <4ECAAEAA.7040102@msstate.edu> Hello, As announced, the due for the lab 10 report is Tuesday 11:59 PM(tomorrow). Thank you, Sungkwang > Is our lab report due tomorrow? > > Nathan Hendrix From kak154 at msstate.edu Mon Nov 21 14:18:44 2011 From: kak154 at msstate.edu (Kyle Kilburn) Date: Mon Nov 21 15:02:38 2011 Subject: [ece3714-02] [ece3714] *Important* Practicum (Final Lab Test) Schedule In-Reply-To: <4ECAAE12.5060008@msstate.edu> References: <4ECAAE12.5060008@msstate.edu> Message-ID: Hi, I told my TA that I wanted to come on Wednesday, but it doesn't look like it was written down, so put me down for Wednesday please. Thanks, Kyle Kilburn On Monday, November 21, 2011, Sungkwang Mun wrote: > Hello, > > I hope everyone has a good Fall break and Thanksgiving holidays. I have a important notice for the final test for the lab (This is not final test for the lecture). The date is scheduled on 11/30 Wednesday 3-6 PM and 12/1 Thursday 5-8 PM. The location will be announced on next Monday. > > As explained, the requirements for the test are Laptop, BASYS board, Breadboard, digital chips and wire. Because of the limit of the devices for a team, both of the team members cannot come to the test at the same time. The schedule for the lab test is attached here as Excel file. Please check your net ID and your friends ID and let me know what date you want to take the test. > > Please notify me the desired dates for you and your lab partner no later than next Monday so that we can prepare properly. If you missed the this final lab test, there won't no make-up test. So please make sure you have a appointment for the final lab test. > > Thank you, > > Sungkwang > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.ece.msstate.edu/pipermail/ece3714/attachments/20111121/d53af7e1/attachment-0001.html From sm655 at msstate.edu Mon Nov 21 15:20:32 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Mon Nov 21 15:20:47 2011 Subject: [ece3714] [Correction] *Important* Practicum (Final Lab Test) Schedule In-Reply-To: <4ECAAE12.5060008@msstate.edu> References: <4ECAAE12.5060008@msstate.edu> Message-ID: <4ECAC0A0.7090504@msstate.edu> Hello, I hope everyone has a good Fall break and Thanksgiving holidays. I have a important notice for the final test for the lab (*This is not final test for the lecture*). The date is scheduled on 11/30 Wednesday 3-6 PM and 12/1 Thursday 5-8 PM. The location will be announced on next Monday. As explained, the requirements for the test are Laptop, BASYS board, Breadboard, digital chips and wire. *Because of the limit of the devices for a team, both of the team members cannot come to the test at the same time _unless each one has all the parts._* The schedule for the lab test is linked below. http://www.ece.msstate.edu/courses/ece3714/Lab_Manual_New/LabTest.xlsx _*Please check the date using your net ID and your friends ID and let me know what date you want to take the test. * _ Please notify me the desired dates for you and your lab partner *no later than next Monday* so that we can prepare properly. *If you missed the this final lab test, there won't no make-up test. So please make sure you have a appointment for the final lab test. *Thank you, Sungkwang -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.ece.msstate.edu/pipermail/ece3714/attachments/20111121/64c9d9cd/attachment.html From sm655 at msstate.edu Tue Nov 22 12:23:56 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Tue Nov 22 12:24:13 2011 Subject: [ece3714] Re: [Correction] *Important* Practicum (Final Lab Test) Schedule In-Reply-To: <4ECAC0A0.7090504@msstate.edu> References: <4ECAAE12.5060008@msstate.edu> <4ECAC0A0.7090504@msstate.edu> Message-ID: <4ECBE8BC.7040203@msstate.edu> Hello, It seems there is a misunderstanding about the lab test (practicum). The lab test is an individual test. That's why each of team member choose different date unless both have all the requirements. Please keep this in mind and choose the date to take the test. I am sorry if I made a confusion in previous email or in the lab. Sungkwang On 11/21/11 PM 03:20, Sungkwang Mun wrote: > Hello, > > I hope everyone has a good Fall break and Thanksgiving holidays. I > have a important notice for the final test for the lab (*This is not > final test for the lecture*). The date is scheduled on 11/30 Wednesday > 3-6 PM and 12/1 Thursday 5-8 PM. The location will be announced on > next Monday. > > As explained, the requirements for the test are Laptop, BASYS board, > Breadboard, digital chips and wire. *Because of the limit of the > devices for a team, both of the team members cannot come to the test > at the same time _unless each one has all the parts._* The schedule > for the lab test is linked below. > > http://www.ece.msstate.edu/courses/ece3714/Lab_Manual_New/LabTest.xlsx > > _*Please check the date using your net ID and your friends ID and let > me know what date you want to take the test. * > _ > Please notify me the desired dates for you and your lab partner *no > later than next Monday* so that we can prepare properly. *If you > missed the this final lab test, there won't no make-up test. So please > make sure you have a appointment for the final lab test. > > *Thank you, > > Sungkwang > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.ece.msstate.edu/pipermail/ece3714/attachments/20111122/4ce180af/attachment.html From sm655 at msstate.edu Sun Nov 27 19:11:14 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Sun Nov 27 19:11:27 2011 Subject: [ece3714] [Update] *Important* Practicum (Final Lab Test) Schedule In-Reply-To: <4ECAC0A0.7090504@msstate.edu> References: <4ECAAE12.5060008@msstate.edu> <4ECAC0A0.7090504@msstate.edu> Message-ID: <4ED2DFB2.8070900@msstate.edu> Hello, The time sheet for the lab test is updated. There are still some students who haven't set the time. Please take a look at them and let me know. http://www.ece.msstate.edu/courses/ece3714/Lab_Manual_New/LabTest.xlsx I will bring the sheet to the class tomorrow. Some tips for the lab test will given too, so please don't miss the class tomorrow. Sungkwang On 11/21/11 PM 03:20, Sungkwang Mun wrote: > Hello, > > I hope everyone has a good Fall break and Thanksgiving holidays. I > have a important notice for the final test for the lab (*This is not > final test for the lecture*). The date is scheduled on 11/30 Wednesday > 3-6 PM and 12/1 Thursday 5-8 PM. The location will be announced on > next Monday. > > As explained, the requirements for the test are Laptop, BASYS board, > Breadboard, digital chips and wire. *Because of the limit of the > devices for a team, both of the team members cannot come to the test > at the same time _unless each one has all the parts._* The schedule > for the lab test is linked below. > > http://www.ece.msstate.edu/courses/ece3714/Lab_Manual_New/LabTest.xlsx > > _*Please check the date using your net ID and your friends ID and let > me know what date you want to take the test. * > _ > Please notify me the desired dates for you and your lab partner *no > later than next Monday* so that we can prepare properly. *If you > missed the this final lab test, there won't no make-up test. So please > make sure you have a appointment for the final lab test. > > *Thank you, > > Sungkwang > -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.ece.msstate.edu/pipermail/ece3714/attachments/20111127/cac8b6c0/attachment.html From sm655 at msstate.edu Sun Nov 27 19:32:40 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Sun Nov 27 19:32:52 2011 Subject: [ece3714] Re: [Update] *Important* Practicum (Final Lab Test) Schedule In-Reply-To: <4ED2DFB2.8070900@msstate.edu> References: <4ECAAE12.5060008@msstate.edu> <4ECAC0A0.7090504@msstate.edu> <4ED2DFB2.8070900@msstate.edu> Message-ID: <4ED2E4B8.1000900@msstate.edu> Hello, If you have lab partner and share the equipments, please discuss with your lab partner first and let me know the time for both of you. Thank you, Sungkwang On 11/27/11 PM 07:11, Sungkwang Mun wrote: > Hello, > > The time sheet for the lab test is updated. There are still some > students who haven't set the time. Please take a look at them and let > me know. > > http://www.ece.msstate.edu/courses/ece3714/Lab_Manual_New/LabTest.xlsx > > I will bring the sheet to the class tomorrow. Some tips for the lab > test will given too, so please don't miss the class tomorrow. > > Sungkwang > > On 11/21/11 PM 03:20, Sungkwang Mun wrote: >> Hello, >> >> I hope everyone has a good Fall break and Thanksgiving holidays. I >> have a important notice for the final test for the lab (*This is not >> final test for the lecture*). The date is scheduled on 11/30 >> Wednesday 3-6 PM and 12/1 Thursday 5-8 PM. The location will be >> announced on next Monday. >> >> As explained, the requirements for the test are Laptop, BASYS board, >> Breadboard, digital chips and wire. *Because of the limit of the >> devices for a team, both of the team members cannot come to the test >> at the same time _unless each one has all the parts._* The schedule >> for the lab test is linked below. >> >> http://www.ece.msstate.edu/courses/ece3714/Lab_Manual_New/LabTest.xlsx >> >> _*Please check the date using your net ID and your friends ID and let >> me know what date you want to take the test. * >> _ >> Please notify me the desired dates for you and your lab partner *no >> later than next Monday* so that we can prepare properly. *If you >> missed the this final lab test, there won't no make-up test. So >> please make sure you have a appointment for the final lab test. >> >> *Thank you, >> >> Sungkwang >> -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.ece.msstate.edu/pipermail/ece3714/attachments/20111127/9babc6de/attachment.html From sm655 at msstate.edu Mon Nov 28 10:17:27 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Mon Nov 28 10:17:48 2011 Subject: [ece3714] Practice for the lab test Message-ID: <4ED3B417.90602@msstate.edu> Hello, The practice sheet for the lab test is attached here. Please use it as you want. On the lab test, you will need to implement the sequential circuits using FSM. Follow the instruction in the document, and try to get the results. The requirements for the test are a BASYS board, a laptop, a breadboard, wire kits and digital chips. Again, the lab test is individual. Please discuss with your lab partner so as to make sure you can bring all requirements for the test. We may not be able to provide the equipments. Thank you, Sungkwang -------------- next part -------------- A non-text attachment was scrubbed... Name: Practice for Lab Test.docx Type: application/vnd.openxmlformats-officedocument.wordprocessingml.document Size: 34612 bytes Desc: not available Url : http://www.ece.msstate.edu/pipermail/ece3714/attachments/20111128/6fc3a2a1/PracticeforLabTest-0001.bin From sm655 at msstate.edu Mon Nov 28 11:59:30 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Mon Nov 28 11:59:51 2011 Subject: [ece3714] Re: lost chips/wire In-Reply-To: References: Message-ID: <4ED3CC02.1020306@msstate.edu> Hello, Kara and his lab partner have left their wire/chip kit in the lab. If anyone has seen it, please let her know. Her email address is knw119@msstate.edu Thank you, Sungkwang On 11/28/11 AM 11:48, Kara Wellman wrote: > SungKwang, > Have you had anyone turn in a wire/chip kit. My lab partner and I went > to get all of our stuff together for the final and noticed that we did > not have our wires and chips. I believe it may have been left in the > lab. If we are unable to find it, is there anything we can do for the > final? > Kara Wellman From sm655 at msstate.edu Mon Nov 28 17:41:49 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Mon Nov 28 17:42:06 2011 Subject: [ece3714] Lab 10 due & grade Message-ID: <4ED41C3D.5000001@msstate.edu> Hello, The due for the lab 10 was last Tuesday, but we heard that there were some difficulties. It was discussed today, and determined to give you *no late-submission penalty (no 20% deduction) if you submit it by tomorrow midnight*(11/29 Tuesday 11:59 PM). *After that, we won't be able to accept the reports. *Please submit the papers by the time. The grades for all labs except lab 10 will be posted online during this week. Please check your grade and let us know if we miss something. All the lab grades are final unless you have a proper excuses (official letter). Here is the contact list for the grades. Lab attendance & Check-off: Sungkwang - sm655@msstate.edu Lab report grade: Keqin (Section1, 9AM) - hz63@msstate.edu Haiqing (Section1, 9AM) - hz63@msstate.edu When you send an email about the grade, please include the section and netID. Thank you, Sungkwang -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.ece.msstate.edu/pipermail/ece3714/attachments/20111128/21af983d/attachment.html From sm655 at msstate.edu Mon Nov 28 17:55:27 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Mon Nov 28 17:55:44 2011 Subject: [ece3714] breadboard and/or part kits In-Reply-To: <4ED3ED06.4020900@ece.msstate.edu> References: <4ED3ED06.4020900@ece.msstate.edu> Message-ID: <4ED41F6F.4030208@msstate.edu> Hello, If you need to buy the lab materials in any reason, please ask MS J. Sungkwang -------- Original Message -------- Subject: Re: Practice for the lab test Date: Mon, 28 Nov 2011 14:20:22 -0600 From: Jane Moorhead Organization: Mississippi State University To: Sungkwang Mun If students are unable to get parts from their partners, have them contact us. We have additional parts kits ($5), breadboards ($20), and wiring kits($10). -------------- next part -------------- Skipped content of type multipart/related From sm655 at msstate.edu Wed Nov 30 11:16:10 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Wed Nov 30 11:16:28 2011 Subject: [ece3714] Lab test Message-ID: <4ED664DA.8020201@msstate.edu> Hello, For the lab tests today and tomorrow, please bring BASYS, breadboard, wire kit and digital chips. Again, the test is implementing circuits on the breadboard using the power of BASYS board as we did in the first few labs. We don't use the Xilinx software. To prepare the test, put 'basys1_breadboard.bit' or 'basys1_breadboard.bit' on your BASYS board using PROM mode in ADEPT software which makes the program stay on the memory. Before coming to test, please take some time to practice to use breadboard. Looking at the specification of the digital chips and actual testing on the breadboard will be very helpful. I attached the practice again. Please try to implement if you haven't done. After the practice, please bring empty breadboard for the test. Thank you, Sungkwang -------------- next part -------------- A non-text attachment was scrubbed... Name: Practice for Lab Test.docx Type: application/vnd.openxmlformats-officedocument.wordprocessingml.document Size: 34656 bytes Desc: not available Url : http://www.ece.msstate.edu/pipermail/ece3714/attachments/20111130/bf17c660/PracticeforLabTest-0001.bin From sm655 at msstate.edu Wed Nov 30 15:06:06 2011 From: sm655 at msstate.edu (Sungkwang Mun) Date: Wed Nov 30 15:06:28 2011 Subject: [ece3714] Bit files for the test Message-ID: <4ED69ABE.8030106@msstate.edu> Hello, These are the bit files that will be used for the test. These are the same files as the one in the lab webpage. Please use these as you want. Thank you, Sungkwang -------------- next part -------------- A non-text attachment was scrubbed... Name: basys1_breadboard.bit Type: application/octet-stream Size: 72742 bytes Desc: not available Url : http://www.ece.msstate.edu/pipermail/ece3714/attachments/20111130/bdbf16b7/basys1_breadboard-0001.obj -------------- next part -------------- A non-text attachment was scrubbed... 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