From morris at ece.msstate.edu Fri Oct 10 16:35:07 2008 From: morris at ece.msstate.edu (Tommy Morris) Date: Fri Oct 10 16:35:10 2008 Subject: [ece4743] Midterm Grades Message-ID: <008901c92b20$10c0d2f0$324278d0$@msstate.edu> Class, I have input mid-term grades for all students. This grade indicates where you stand after the first test and through lab 4. I have applied a curve. Also, I have added several items to the class website. homework 2 solutions homework 3 homework 3 solutions Have a good weekend. Thomas Morris, Ph.D. Assistant Professor Electrical and Computer Engineering Mississippi State University 233 Simrall Hall - (662)325-3199 -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.ece.msstate.edu/pipermail/ece4743/attachments/20081010/8226c577/attachment.html From morris at ece.msstate.edu Mon Oct 13 18:58:08 2008 From: morris at ece.msstate.edu (Tommy Morris) Date: Mon Oct 13 18:58:20 2008 Subject: [ece4743] Lab 6 & 7 Update Message-ID: <30908172.105651223942288521.JavaMail.root@zimbra.ece.msstate.edu> Dear Students, I have decided to delay lab 7 1 week. You may start Lab 7 next week. Also, you may turn in your lab 6 next week when you meet for Lab 7. Also, there is an error in both Lab 6 (in the raster memory portion) and in Lab 7 (since it reuses this code). I will upload corrected handoffs tomorrow morning. I will send a new email tomorrow after uploading the corrected handoffs. Thanks, Thomas Morris, Ph.D. Assistant Professor Electrical and Computer Engineering Mississippi State University 233 Simrall Hall - (662)325-3199 From morris at ece.msstate.edu Tue Oct 14 14:31:49 2008 From: morris at ece.msstate.edu (Tommy Morris) Date: Tue Oct 14 14:31:52 2008 Subject: [ece4743] Lab 6 & 7 Message-ID: <000001c92e33$80aa3d20$81feb760$@msstate.edu> Dear Students, I have uploaded a new copies of Lab 6 and 7. There were 2 basic errors. First, there were verilog and vhdl copies of the vga_buffer and vga_sync files. The VHDL files are the correct files to use. In these lab handoffs I have removed the verilog copies since they are no correct. Second, I had inadvertently made the vid_rom file too large. However to my not declaring a wire as [1:0] the Xilinx synthesis tool optimized my vid_rom to 1-bit wide and it subsequently fit in memory. I have updated the vid_rom in the new handoffs to be a size which actually fits in the memory on the FPGA. If you were getting 1.5 Snoopys switching to the VHDL files should get you 1 Snoopy. If you were getting errors that the design was too large, the new vid_rom will fix that. I also added a lot of description to Lab 6 to help understand how to address the ROMs. Hopefully, this new description will help. For Lab ,6 I added a romconnect.v and lab6.sch which connects the vga_sync, and vga_buffer to the romconnect module. You can limit your changes to the romconnect.v to get this lab working. Just instantiate the needed ROM and then add you addressing and color mapping logic. Lab 6/7 material will not be on tomorrow's exam. What if I want to start fresh on my lab with these new handoffs? 1. Switch from using the vga_sync.v and vga_buffer.v to using vga_syn.vhd and vga_buffer.vhd. 2. Copy and replace all files in the new handoff with the prefix "vid_rom" to your working directory. This should allow you to keep your old working directory. Alternatively, you can work in the new "Lab6files" directory can copy your logic (from your old working directory) to the romconnect.v file. Open Lab6.ise. Double click romconnect.v and edit to add your logic. Same concept for Lab 7. Thanks, Thomas Morris, Ph.D. Assistant Professor Electrical and Computer Engineering Mississippi State University 233 Simrall Hall - (662)325-3199 -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.ece.msstate.edu/pipermail/ece4743/attachments/20081014/9725f932/attachment.html From morris at ece.msstate.edu Wed Oct 15 13:06:49 2008 From: morris at ece.msstate.edu (Tommy Morris) Date: Wed Oct 15 13:06:52 2008 Subject: [ece4743] Updated Homework #2 and #3 to fix errors Message-ID: <004d01c92ef0$cb72b1d0$62581570$@msstate.edu> Class, I fixed the errors in the homework solutions discussed in class on Monday. I highlighted the changes in red text so that you can see them easily. Thanks, Thomas Morris, Ph.D. Assistant Professor Electrical and Computer Engineering Mississippi State University 233 Simrall Hall - (662)325-3199 -------------- next part -------------- An HTML attachment was scrubbed... URL: http://www.ece.msstate.edu/pipermail/ece4743/attachments/20081015/9350e239/attachment.html