Publications

2004

• J.S. Davis and L.T. Bullen, "TDR Measurement Techniques for Package Variations", Napa KGD Packaging and Test Workshop, Napa, CA, September 2004.  (To appear)
  
• J.W. Bruce, "Design Methodology Suitable for Team-based Embedded Systems Education", ASEE Computers in Education Journal, vol. 14, no. 3, pp. 41-54,  July 2004.  
• J.W. Bruce, "Design Inspections and Software Product Metrics in an Embedded Systems Design Course", Proc. of the ASEE Annual Conference and Exposition, Session 1620, Salt Lake City, UT, June 2004.
• J.W. Bruce and L.A. Hathcock, "Maintenance and Monitoring Object Models for High-Availability Network Appliances", IEEE Trans.  on Consumer Electronics, vol. 50, no. 2, pp. 472-477,  May 2004. 
• L.M. Bruce and J.W. Bruce, "Maximizing Your Productivity as a Junior Faculty Member: Balancing Research, Teaching, and Service", Proc. of the ASEE Annual Conference and Exposition, Session 1475, Salt Lake City, UT, June 2004.
• J.W. Bruce and L.M. Bruce, "Maximizing Your Productivity as a Junior Faculty Member: Being Effective in the Classroom", Proc. of the ASEE Annual Conference and Exposition, Session 2275, Salt Lake City, UT, June 2004.
• C. Traver, J. Harden, K. Goodjohn, and R. Reese, "Asynchronous Rate Divider and Multiplier Designs for LEDR Logic," IEE Electronics Letters, vol. 40, no. 7,  pp. 414-415, April 2004.
  
• R. Reese, M. Thornton and C. Traver, "Two-phase micropipeline control wrapper with early evaluation", IEE Electronics Letters, vol. 40, no. 6, pp. 365-366, March 2004.
  
• R. Reese, M. Thornton and C. Traver, "Fast two-phase micropipeline control wrapper for standard cell implementation", IEE Electronics Letters ,vol. 40, no. 4, pp. 227-229, Feb 2004.
  
• J.W. Bruce, J.C. Harden, and R.B. Reese, "Cooperative and Progressive Design Experience for Embedded Systems", IEEE Trans.  on Education, vol. 47, no. 1, pp. 83-92, Feb. 2004.

2003

• M. Morgan and  J.W. Bruce, "The CRL gateway: A new way to build logic functions", IEEE Potentials, vol. 22, no. 5, pp. 8-11,  Dec. 2003.
• D. C. Keezer, J. S. Davis, S. Bezos, D. Minier, M. C. Caron, K. Bergman, O. Liboiron-Labouceur, "Low-Cost Strategies for Testing Multi-Gigahertz SOPs and Components", Electronics Packaging Technology Conference, pp. 410-414, Singapore, December 2003.
• J.W. Bruce, M.A. Gray, and R.F. Follett, "Personal Digital Assistant (PDA) Based I2C Bus Analysis", IEEE Trans.  on Consumer Electronics, vol. 49, no. 4, pp. 1482-1487,  Nov. 2003. 
• J.S. Davis, D.C. Keezer, O. Liboiron-Ladouceur, K. Bergman, "Application and Demonstration of a Digital Test Core: Optoelectronic Test Bed and Wafer-level Prober", Proc. International Test Conference, pp. 166-174, Charlotte, NC, October 2003.
• D.C. Keezer, J.S. Davis, M. Haris, S. Bezos, D. Minier, M.C.Caron, K. Bergman, O. Liboiron-Labouceur, "Recent Advances in Low-Cost Multi-GigaHertz Testing", Napa KGD Packaging and Test Workshop, Napa, CA, September 2003.
  
• J.W. Bruce, "Design Methodology Suitable for Team-based Embedded Systems Education", Proc. of the ASEE Annual Conference and Exposition, Paper 83, Session 1620, Nashville, TN, June 2003. 
• R.S. Winton, and W.A. King, "Semiconductor Device Instruction by Means of Circuit Simulation Constructs", Proc. of the ASEE Annual Conference and Exposition, Nashville, TN, June 2003.  (To appear)
• J.S. Davis, D.C. Keezer, K. Bergman, O. Liboiron-Ladouceur, "Application of a Digital Test Core to a Test Bed for Bit-Parallel Optoelectronic Communications", International Mixed-Signal Test Workshop,pp. 113-118, Sevilla, Spain, June 2003.
• R. Reese, M. Thornton and C. Traver, "A Coarse-grained Phased Logic CPU", Proc. Ninth International Symposium on Advanced Research in Asynchronous Circuits and Systems, pp 2-13, Vancouver, BC, Canada, May 2003.
• K. Fazel, M. Thornton and R. Reese, "PLFire: A Visualization Tool for Asynchronous Phased Logic Designs", Proc. IEEE/ACM Conf. On Design, Automation and Test in Europe, pp 1096-1097, March 2003.
• R. Reese, M. Thornton and C. Traver, "A Fine-grained Phased Logic CPU", Proc. IEEE Computer Society Annual Symposium on VLSI, pp 70-79, Tampa, FL, February  2003.
  
  

2002

• D.C. Keezer and J.S. Davis, S. Ang, M. Rotaru, "A Test Strategy for Nanoscale Wafer Level Packaged Circuits", Proc. Electronics Packaging Technology Conference, pp. 175-179, Singapore, December 2002.
• J.S. Davis and D.C. Keezer, "Multi-Purpose Digital Test Core Utilizing Programmable Logic", Proc.International Test Conference, pp. 438-445, Baltimore, MD, October 2002.
• D.C. Keezer and J.S. Davis, "An FPGA-Based Digital Logic Core for Embedded Test Applications", 9th Annual KGD Workshop, Napa, CA, September 2002.
• R.B. Reese, S. Sikandar-Gani, "Control versus Compute Power within a LEDR-style Self-timed Multiplier", Proc. IEEE Midwest Symposium on Circuits and Systems, pp 302-305, Tulsa, OK, August 2002.
  
• J.W. Bruce, J.E. Creekmore, S.R. Porter, R.P. King, and B.J. Blalock, "Adaptive Design Method for Efficient Direct Digtal Synthesis", Proc. IEEE Midwest Symposium on Circuits and Systems, pp. 545-548, Tulsa, OK, August 2002.
• J.A. Bell and J.W. Bruce, "CMOS Current Mode Interpolating Flash Analog to Digital Converter", Proc. of the IEEE Midwest Symposium on Circuits and Systems, pp. 363-366, Tulsa, OK, August 2002.
• J. Harden, and M. Lane, "Web-Based Tools for Assessment Automation," Proc. ASEE Annual Conference & Exposition, Montreal, Quebec, Canada, June 16-19, 2002.
• J.W. Bruce, M.A. Thornton, L. Shivakumaraiah, P.S. Kokate, and X. Li, "Efficient Adder Circuits Based on a Conservative Reversible Logic Gate," Proc. of the IEEE Computer Society Annual Symposium on VLSI, pp. 83-88, Pittsburgh, Pennsylvania, April 2002.
• M.A. Thornton, K. Fazel, R.B. Reese, and C. Traver, "Generalized Early Evaluation in Self-Timed Circuits", Proc. IEEE/ACM Conf. Design Automation and Test in Europe, pp. 255-259, Paris, March, 2002.

2001

• C. Traver, R. B. Reese, M. A. Thornton, "Cell Designs for Self-timed FPGAs", Proc. of the 2001 ASCI/SOC Conference, pp. 175-179, September 2001.
• R. B. Reese, M. A. Thornton, and C. Traver, "Arithmetic Logic Circuits using Self-timed Bit-Level Dataflow and Early Evaluation", Proc. of the Conference on Computer Design, pp. 18-23, September 2001.
• J.W. Bruce, "Nyquist-rate digital to analog converter architectures," IEEE Potentials, vol. 20, no. 3, pp. 24-28, August 2001.
• J.A. Bell, J.W. Bruce, B.J. Blalock, and P. Stubberud, "CMOS current mode flash analog to digital converter," Proc. of the IEEE Midwest Symposium on Circuits and Systems, pp. 272-275, Dayton, Ohio, August 2001.
• J.E. Creekmore, S.R. Porter, J.W. Bruce, and B.J. Blalock, "Direct digital frequency synthesis using nonlinear digital-to-analog conversion," Proc. of the IEEE Midwest Symposium on Circuits and Systems, pp. 897-900, Dayton, Ohio, August 2001.
• J.W. Bruce, B. Steadman, and P. Stubberud, "Generalized cube based dynamic element matching algorithms for DACs", IEE Electronics Letters, vol. 37, no. 8, pp. 485-487, April 2001. 
• R. Barnes, N. Younan, J. Harden, “Spectral Analysis of Timestamp Data on Unsynchronized Computer Systems,”  Proc. of the Southeastern Symposium on System Theory, pp. 305-308, March 2001.
• P. A. Stubberud and J.W. Bruce, "An analysis of dynamic element matching flash digital to analog converters," IEEE Trans. on Circuits and Systems II, vol. 48, no. 2, pp. 205-213, Feb. 2001.
• S. A. Jackson, J. Killens, and B. J. Blalock, "A programmable current mirror for analog trimming using single-poly floating gate devices in standard CMOS technology," IEEE Trans. on Circuits and Systems II, vol. 48, no. 1, pp. 100-102,  Jan. 2001.

2000

• B. J. Blalock, H. W. Li, P. E. Allen, and S. A. Jackson, "Body-Driving as a Low-Voltage Analog Design Technique for CMOS Technology," Proc. 2000 Southwest Symp. on Mixed-Signal Design, 2000, pp. 113-118. (invited paper)
• S. A. Jackson and B. J. Blalock, "An Active Substrate Driver for Mixed-Voltage SOI Systems On A Chip," Proc. 2000 Southwest Symp. on Mixed-Signal Design, 2000, pp. 83-86. 
• J.W. Bruce and P. Stubberud, "A comparison of hardware efficient dynamic element matching networks for digital to analog converters," Proc. of the 2000 Midwest Symposium on Circuits and Systems, East Lansing, Michigan, August 2000. 
• P. Stubberud and J.W. Bruce, "An analysis of dynamic element matching algorithms for analog to digital converters," Proc. of the 2000 Midwest Symposium on Circuits and Systems, East Lansing, Michigan, August 2000. 
• J.W. Bruce and P. Stubberud, "An analysis of analog to digital conversion and harmonic distortion," Proc. of the 2000 Midwest Symposium on Circuits and Systems, East Lansing, Michigan, August 2000.
• R. Reese, and C. Traver, "Synthesis and Simulation of Phased Logic Systems", Technical Report MSSU-COE-ERC-00-09, MSU/NSF Engineering Research Center, June 2000.
• J.W. Bruce, "Dynamic element matching techniques for data converters," Ph.D. dissertation, Department of Electrical and Computer Engineering, University of Nevada Las Vegas, 2000. 

1999

• J.W. Bruce, "Meeting the analog world challenge: Nyquist rate analog to digital converter architectures," IEEE Potentials, vol. 17, no. 5, pp. 36-39, January 1999.
• B. J. Blalock and S. A. Jackson, "A 1.2-V CMOS Four-Quadrant Analog Multiplier," in Proc. 1999 Southwest Symp. on Mixed-Signal Design, 1999, pp. 1-4. 
• J.W. Bruce and P. Stubberud, "An analysis of harmonic distortion and integral nonlinearity errors in DACs," Proc. of the 1999 Midwest Symposium on Circuits and Systems, pp. 470-473, Las Cruces, New Mexico, August 1999.
• P. Stubberud and J.W. Bruce, "An analysis of stochastic dynamic element matching DACs," Proc. of the 1999 Midwest Symposium on Circuits and Systems, pp. 481-484, Las Cruces, New Mexico, August 1999.
• P. Stubberud and J.W. Bruce, "A frequency analysis of stochastic dynamic element matching flash digital-to-analog converters," Proc. of the International Conference on Systems Engineering XIV, pp. EE13-18, Las Vegas, Nevada, August 1999. 
• H. Lavana, F. Brglez, R.B. Reese, "User-Configurable Experimental Design flows on the Web: The ISCAS'99 Experiments", Proc. of International Symposium on Circuits and Systems, Orlando, FL, May 1999.
• P. Stubberud and J.W. Bruce, "Exposing Undergraduates to Collaborative Engineering Design Teams," Proc. of the Annual Meeting of the ASEE Pacific Southwest Section, pp. 79-86, Las Vegas, Nevada, March 1999.
• J. Harden and W. Francis, “GPS-Based Instrumentation for Distributed Computing Systems,”  Proc. of  The Southeastern Symposium on System Theory, March 1999.

1998

• D.C. Keezer, K. E. Newman, and J.S. Davis, "Improved Sensitivity for Parallel Test of Substrate Interconnections", Proc. International Test Conference, pp 228-233, October 1998.
• J. Robinson and J. Harden, “Mars Pathfinder Motivates Student Project,” Wind River’s Scholar, vol. 3. (http://www.windriver.com/univ/html/scholar_fall98.html), Fall 1998.
• K.E. Newman, D.C. Keezer, and J.S. Davis, "Highly Sensitive Parallel Test of Substrate Electrical Interconnections", Advanced Technology Workshop on MCM Test V, September 1998.
• K.E. Newman, D.C. Keezer, and J. S. Davis, A Parallel Test Method for MCM Substrate Interconnection Networks, International Journal of  Microcircuits and Electronic Packaging, vol. 21, no. 7, pp. 197-204, August 1998.
  
• J. Harden, D. Reese, and G. Henley, “UltraScope: Precision Instrumentation in a Global Context,” MSU ERC Field Points, Vol. 5, No. 3, Summer 1998.
• B. J. Blalock, P. E. Allen, and G. A. Rincon-Mora, "Designing 1-V Op Amps using Standard Digital CMOS Technology," IEEE Trans. on Circuits and Systems II, vol. 45, no. 7, pp. 769-780, July 1998. 
• S. A. Jackson and B. J. Blalock, "A CMOS Mixed-Signal Simultaneous Bidirectional Signaling I/O," in Proc. 1998 IEEE Midwest. Symp. Circuits Syst, 1998, pp. 37-40. 
• J.W. Bruce and P. Stubberud, "Switching circuit network topologies for dynamic element matching data converters," The 105th Convention of the Audio Engineering Society, (1998 Sept.), preprint 4773. 
• J.W. Bruce and P. Stubberud, "Generalized cube networks for implementing dynamic element matching digital-to-analog converters," Proc. of the 1998 Midwest Symposium on Circuits and Systems, pp. 522-525, Notre Dame, Indiana, August 1998. 
• P. Stubberud, J.W. Bruce and B. Steadman, "A DAC architecture with a hardware efficient dynamic element matching network," Proc. of The Second International Workshop on Design of Mixed-Mode Integrated Circuits and Applications, pp. 9-12, Guanajuato, Mexico, July 1998.
• J.W. Bruce, P. Stubberud and A. Iyer, " Range estimation and object identification with a single camera machine vision system," Proc. of the International Conference on Systems Engineering XIII, pp. 253-259, Wroclaw, Poland, September 1998. 
• P. Stubberud and J.W. Bruce, "An LMS algorithm for training single layer globally recursive neural networks," Proc. of IEEE Int'l Joint Conference on Neural Networks, pp. 2214-2217, Anchorage, Alaska, May 1998. 

1997

• R.B. Reese, C. McCloslkey, V. Sanders., "Redesign of a Generic VHDL Model Template for SRAMs ", Rapid Systems Prototyping with VHDL, Proceedings of VHDL International Users Forum, Arlington, VA, pp. 122-125, October 1997.
• R.B. Reese, D. Brown., "VHDL Modeling and Tutoring Efforts by Mississippi State University ", Rapid Systems Prototyping with VHDL, Proceedings of VHDL International Users Forum, Arlington, VA, pp. 179-182, October 1997.
• R. Koteshwar, J.  Harden, D. Reese, and A. Saha, "High Performance Multi-Block Multi-Grid Parallel Solver for Navier-Stokes Equations," Proc. of the Simulation MultiConference, Atlanta, GA, pp. 9-14, April 1997.

1996

• J.S. Calhoun, V. K. Madisetti, R. B. Reese, T. Egolf., "Developing and Distributing Component-Level VHDL Models", Journal of VLSI Signal Processing, vol 15, pp. 111-126, 1996.
• B. J. Blalock, "A 1-Volt CMOS Wide Dynamic Range Operational Amplifier," Ph.D. Dissertation, School of ECE, Georgia Tech, Atlanta, GA, 1996. 
• B. J. Blalock and P. E. Allen, "A One-Volt, 120-µW, 1-MHz OTA for Standard CMOS Technology," in Proc. IEEE International Symp. Circuits and Syst, pp. 305-307, 1996. 
• L.M. Bruce, R.R. Adhami, and J.W. Bruce, "Appropriate scales when using wavelets for feature extraction," Intelligent Engineering Systems Through Artificial Neural Networks vol. 6, Proc. of Artificial Neural Networks in Engineering 1996, (Dagli et al,eds.), St. Louis, Missouri, pp. 507-512, November 1996.
• L.M. Bruce, R.R. Adhami, and J.W. Bruce, "Wavelets for shape recognition with applications to mammography," Intelligent Engineering Systems Through Artificial Neural Network vol. 6, Proc. of Artificial Neural Networks in Engineering 1996, (Dagli et al,eds.), St. Louis, Missouri, pp. 653-658, November 1996.
• D. Reese, H. Ravishandran, J. Harden, G. Henley, M. Evans, S. Kadambi, R. Koteshwar, and L. Burton, "A Hybrid Approach for Tracing MPI Programs", Proc. of the Third Scalable parallel Libraries Conference, October 1996.
• R. Koteshwar, A. Saha, J. Harden, and D. Reese, "Efficient Parallel Multigrid Solver for Navier-Stokes Equations," Proc. IASTED International Conference on Parallel and Distributed Computing and Systems, Chicago, Il., pp. 452-456, October 1996.
• R.B. Reese, and V. Sanders, "A VHDL Modeling Approach to the Xilinx 4000 Series FPGA", Proc. VHDL International User's Forum, Durham, NC, October 1996.
• R.B. Reese, J.S. Calhoun., "Mississippi State Develops on-line FPGA Model Generator", RASSP Digest, vol. 3, pp 39-41, September 1996.
• D. H. Linder and J. Harden, "Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry," IEEE Transactions on Computers, vol. 45, pp. 1031-1044, September 1996.
• R. Koteshwar, A. Saha, and J. Harden, "High Performance Parallel Multigrid Solver,"  Maui High Performance Computing Center Application Briefs, pp. 1-3, and 1-10, 1996.
• R. Koteshwar, A. Saha, and J. Harden, "Development of a Multiblock Parallel Solver for the Three-Dimensional Incompressible Navier-Stokes Equations," Parallel CFD 96, May, 1996.

1995

• J. Harden and N. Strader, "Manufacturing Yield Evaluation for VLSI/WSI Systems," in Architectural Yield Optimization for WSI, edited by Bruno Ciciani, IEEE Computer Society Press, pp. 287-309, 1995.
• J. Harden, C. Alexander, D. Reese, M. Evans, and C. Hudnall, "In Search of a Standards-Based Approach to Hybrid Performance Monitoring."  Special joint issue on Evaluation Tools for Parallel and Distributed Systems of  Institute of Electrical and Electronics Engineers (IEEE) Parallel and Distributed Technology and Computer, Winter, 1995.
• R.B. Reese, "Chapter 10.2.1: VHDL Synthesis" in Microsystems Technology

for Multimedia Applications - An Introduction, Bing Sheu et al, eds., IEEE
Press, pp. 675- 684, 1995.
• B. J. Blalock and P. E. Allen, "A Low-Voltage, Bulk-Driven MOSFET Current Mirror for CMOS Technology," in Proc. 1995 IEEE Int. Symp. Circuits Syst, 1995, pp. 1972-1975. 
• P. E. Allen, B. J. Blalock, and G. A. Rincon, "A 1-Volt CMOS Op Amp Using Bulk-Driven MOSFETs," in Dig. 1995 IEEE Int. Solid-State Circuits Conf., Feb. 1995, pp. 192-193. 
• P. E. Allen, B. J. Blalock and G. A. Rincon, "Low-Voltage Analog Circuits Using Standard CMOS Technology," in Proc. 1995 IEEE Int. Symp. Low Power Design, 1995, pp. 209-214.
• P. E. Allen, B. J. Blalock, and S. W. Milam, "Active filters using low-gain amplifiers," in The Circuits and Filters Handbook, CRC press, Inc., 1995. 
• S. Kadambi, J. Harden, and D. Linder, "High-Performance Disk I/O in a Bus-Based System," Proc. of the Southeastern Symposium on System Theory, pp. 231-235, March 1995.
• S. Kadambi and J. Harden, "Accelerating CFD Applications by Improving Cached Data Reuse," Proc. of the Southeastern Symposium on System Theory, pp. 120-124, March 1995.
• J.G. Thompson and J. Harden, "Standards-Based Hybrid Probe Instrumentation for Multiprocessor Computing Systems," Proc. of the Southeastern Symposium on System Theory, pp. 114-119, March 1995.

1994

• D. Linder, J. Harden, "Access Graphs: A Model for Investigating Memory Consistency," IEEE Transactions on Distributed and Parallel Computing, vol. 5, January 1994.
• J.Harden, C. Alexander, and D. Reese, "Near-Critical Path Analysis of Program Activity Graphs," Proc. International Workshop on Modeling, Analysis and Simulation of Computer and Telecommunications Systems, Durham, North Carolina, 1994.

1993

1992

• Reese, R., "Schematic Entry" in Anatomy of a Silicon Compiler, Robert W. Brodersen, ed., Kluwer Academic Publishers, 1992.
• R.B Reese, and B. Boes, "Standard Cell Design" in Anatomy of a Silicon Compiler, Robert W. Brodersen, ed., Kluwer Academic Publishers, 1992.
• R.B. Reese, "Appendix B: Training and Distribution" in Anatomy of a Silicon Compiler, Robert W. Brodersen, ed., Kluwer Academic Publishers, 1992.
• R.B. Reese, "Use of VHDL Synthesis in an Advanced Digital Design Course", Proc. Fifth Annual IEEE International ASIC Conference & Exhibit, Rochester NY,  September 1992.
• R.B. Reese, "Use of VHDL Synthesis in an Advanced Digital Design Course",

Proc. IEEE Southeastcon, April 1992.
• J. Harden, D. Reese, F. To, D. Linder, C. Borchert, G. Jones, "A Performance Monitor for the MSPARC Multicomputer," Proc. IEEE Southeastcon, April 1992.
• J.Harden, T. Teh, and J. D. Trotter, "Integrating Gate Array Design Into a Standard Cell CAD Environment," Proc. IEEE Southeastcon, April 1992.
• J. Harden, J. Kidd, and D. Linder, "Probe Acquisition for the MSPARC Hybrid Monitor," Proc. IEEE Southeastcon, April 1992.

1991

• D. Linder and J. Harden, "An Adaptive and Fault Tolerant Wormhole Routing Strategy for k-ary n-cubes," IEEE Trans. Computation, January 1991.
• J. Harden, J. Hwith, D. Reese, and F. To, "Hybrid Performance Monitor for the MSPARC Multicomputer," Ninth Annual Sun User Group Conference, San Jose, California, December 1991.
• J. Harden and R.B. Reese, "Efficient Use of a Behavioral Simulator in an Introductory Computer Architecture Course," Microelectronic System Education Conference & Exposition, San Jose, California, June 1991.
• J. Harden, F.S. To,  R.K. Matthes, "Parallel Distributed Data Acquisition/Analysis System," International Summer Meeting, American Society of Agricultural Engineers, Albuquerque, New Mexico, June 1991.
• F. To, J. Harden, and J. K. Owens, "Simulation of a Block Mode Adaptive Message Router for a Mesh Network," Western MultiConference on Computer Simulation, January 1991. 

1990

1989

• J. Harden and N. Strader, "Architectural Yield Optimization,"  in Wafer Scale Integration, Norwell, MA:  Klewer Academic Publisher, pp. 57-118, 1989.
• L. Jackson, and J. Harden, "The Use of a Separate Input/Output Processor in the MADEM Multicomputer," Proc. Southeast Conference ACM, Atlanta, GA, April 1989.
• J. Harden, B. Tebbs, and J. Wang, "A High-Level WSI Yield Simulation System," Proc. International Conference WSI, January 1989.

1988

• J. Harden and N. Strader, "Architectural Yield for WSI," IEEE Trans. Computation, vol. 37, no. 1, January 1988.

1987

• J. Harden, "MC68020 Based Advanced Microprocessor Course at Mississippi State University," The University Newsletter, vol. 4, 1987.

1986

• J. Harden, "Comments on Fault-Tolerant Design for VLSI:  Effect of Interconnect Requirements on Yield Improvement of VLSI Design," Proc. IEEE, vol. 74, no. 3, March 1986.

1985

1984

• J. Harden, "Discussions Following Papers and Presentations Contained in II, III, and IV,"  Proc. SRC Wafer Scale Integration Workshop Proceedings, no. SRC-012 September 1984.