--- linuxppc_2_4_devel.orig/arch/ppc/platforms/rpxclassic.h	Thu Sep 11 14:23:38 2003
+++ linuxppc_2_4_devel/arch/ppc/platforms/rpxclassic.h	Fri Oct 17 16:21:53 2003
@@ -73,6 +73,14 @@
 #define BCSR2_QSPACESEL		((uint)0x00004000)
 #define BCSR2_FETHLEDMODE	((uint)0x00000800)	/* CLLF */
 
+#define BCSR4_ADDR		 ((uint)0xfa400004) /* BCSR4 for the EP862 board */
+#define BCSR4_SCC_DTR           ((uint)0x40000000)
+#define BCSR4_SCC_ENXCVR0       ((uint)0x10000000)
+#define BCSR4_EN_SCC_RI_IRQ     ((uint)0x08000000)
+#define BCSR4_SCC_S0            ((uint)0x04000000)
+#define BCSR4_SCC_S1            ((uint)0x02000000)
+#define BCSR4_SCC_S2            ((uint)0x01000000)
+
 /* define IO_BASE for pcmcia, CLLF only */
 #if !defined(CONFIG_PCI)
 #define _IO_BASE 0x80000000
--- linuxppc_2_4_devel.orig/arch/ppc/8xx_io/uart.c	Thu Sep 11 14:23:51 2003
+++ linuxppc_2_4_devel/arch/ppc/8xx_io/uart.c	Fri Oct 17 16:30:34 2003
@@ -2743,6 +2742,29 @@
 #endif
 #endif
 
+   /* This is actually for the EP862 board
+   */
+#ifdef CONFIG_RPXCLASSIC
+	/* Map SCC2(B) to J5 Serial port
+	*/
+	*((volatile uint *)BCSR4_ADDR) &= ~(BCSR4_SCC_S0 | BCSR4_SCC_S1 | BCSR4_SCC_S2 | BCSR4_SCC_ENXCVR0 | BCSR4_SCC_DTR | BCSR4_EN_SCC_RI_IRQ);
+	*((volatile uint *)BCSR4_ADDR) |= BCSR4_SCC_S0;
+	*((volatile uint *)BCSR4_ADDR) |= BCSR4_SCC_ENXCVR0;
+	printk("\nBCSR4 set...\n\n");
+
+	/* Configure SCC2, SCC3, and SCC4 instead of port A parallel I/O.
+	 */
+	immap->im_ioport.iop_papar |= 0x000c;  /* set PAPAR[12,13] */
+	immap->im_ioport.iop_padir &= ~0x000c; /* clear PADIR[12,13] */
+	immap->im_ioport.iop_paodr &= ~0x000c; /* clear PAODR[12,13] */
+
+	immap->im_ioport.iop_pcpar |= 0x0002;  /* set PCPAR[14] */
+/*	immap->im_ioport.iop_pcso |= 0x00c0;*/ /* set PCSO[8,9] */  /* this breaks it...why??? */
+
+	immap->im_ioport.iop_pcpar &= ~0x00c0; /* clear PCPAR[8,9] */
+	immap->im_ioport.iop_pcdir &= ~0x00c2; /* clear PCDIR[8,9,14] */
+#endif
+
 	for (i = 0, state = rs_table; i < NR_PORTS; i++,state++) {
 		state->magic = SSTATE_MAGIC;
 		state->line = i;