BPM

From Ece

Team BPM

Captain: Chris Butler

Member: Barbara Pilate

Member: Dontavius Morrissette

Goal

To design and simulate a 16-bit pipelined RISC processor. The simulation of this processor will be built out of C++ source code with the ability to execute fifteen instructions. We will use the rising edge triggered as our clocking methodology. For our registers file, there will be 16 registers included; each register in the file being 16-bits wide.

Scheduled Meetings

-Thursday Nov. 3: 3:30-5:30 pm.
-Tuesday Nov. 8: 3:30-5:30 pm.
-Thursday Nov. 10: 3:30-5:30 pm.
-Tuesday Nov. 15: 3:30-5:30 pm.
-Thursday Nov. 17: 3:30-5:30 pm.
-Tuesday Nov. 29: 3:30-5:30 pm.

Updates

Tuesday Nov. 15

-Confirmed schematic of datapath
-Setup repository on Google Code
-Converted instruction into binary
-Began implementation of processor functions

Thursday Nov. 17

-Got code in data memory and instruction memory
-Initialized registers
-Start working on processor functions

Teusday Nov. 29

-Got majority of processor functions coded
-Having trouble with getting correct output
-Currently debugging

Project Files

BPM Proposal [1]

BPM Datapath [2]

BPM Source Code [3]