Card Reader
From Ece
Team: Sudden Death
Our goal is to create a magnetic stripe card reader capable of displaying the card’s information to the screen.
Contents |
Team Members
- Thomas Donaldson -- Coordinator, Checker
- Eugene Sandberg -- Coordinator, Recorder
Phase 1(Updated for Phase 2)
Introduction
“A magnetic stripe card is a type of card capable of storing data by modifying the magnetism of tiny iron-based magnetic particles on a band of magnetic material on the card. The magnetic stripe, sometimes called a magstripe, is read by physical contact and swiping past a reading head. Magnetic stripe cards are commonly used in credit cards, identity cards, and transportation tickets.”(Wikipedia)
“In most magnetic stripe cards, the magnetic stripe is contained in a plastic-like film. The magnetic stripe is located 0.223 inches (5.66 mm) from the edge of the card, and is 0.375 inches (9.52 mm) wide. The magnetic stripe contains three tracks, each 0.110 inches (2.79 mm) wide. Tracks one and three are typically recorded at 210 bits per inch (8.27 bits per mm), while track two typically has a recording density of 75 bits per inch (2.95 bits per mm). Each track can either contain 7-bit alphanumeric characters, or 5-bit numeric characters.” (Wikipedia)
Concept
An external card reader and a VGA monitor will be connected to the Spartan3E FPGA. When a card is swiped through the reader the FPGA will output the card’s information to the VGA monitor. The FPGA will need to parse the data and format it appropriately for display.
The external card reader is connected to the FPGA via a PS2 cable which will power the reader and provide a connection for communication. The VGA monitor will be connected via a VGA cable and is powered by a standard 120V wall outlet.
Proposed Work
- The card reader will stream the swiped information to the FPGA.
- The signal processing module will interpret the data and send it to a memory interface.
- A memory interface will store the card's information.
- A display module will display the contents of the memory to a VGA monitor.
Thomas Donaldson will design a module to serve as the intermediate between the pre-existing ps2decode module and the memory. This module will parse the characters, removing any non-useful formatting characters and pass the card stripe's information into memory.
Eugene Sandberg will design a module to serve as the intermediate between the memory and the pre-existing vga_sync module. This module will read the memory and properly format the information for output.
Figure 1 - Basic block diagram
Required Parts
- KANESWIPE Magnetic Card Reader
- Reads tracks 1, 2, and 3
- PS2 interface
- Cost: $50
- Supplier: http://store.kanecal.net/
- Product Code: KCGIT2
- Datasheet
- Expected: April 14, 2008
- VGA cable and monitor
- Already available
- Xilinx Spartan 3E FPGA
- Already available
Expected Deliverables
Using the parts listed, we will construct a fully functional magnetic card reader and be able to display the information encoded on the card's stripe to the VGA monitor.
Phase 3
Review of Proposed Work
Overall, the project design has expanded. After careful inspection, the project needed more modules for proper functioning.
1. Data from the ps2core module needs to be groomed. Developer: Thomas Donaldson 2. The signal processing module will interpret the data and send it to a memory interface. Developer: Thomas Donaldson 3. A memory interface will store the card's information. Developer: Eugene Sandberg 4. A display module will display the contents of the memory to a VGA monitor. Developer: Eugene Sandberg 5. A simple module to scale back the clock for VGA output. Developer: Eugene Sandberg
Module Descriptions
display
This module handles the conversion from ASCII to an output code for the char_rom module. Whenever the write line is low, this module passes an address to the RAM which returns an ASCII character. The module then converts this character into an output code that is sent to the char_rom module.
Inputs:
clk: 100 MHz clock signal
row(2:0): Which row of the output we are on
column(2:0): Which row of the output we are on
din(7:0): The data in the RAM location specified
load: A signal from the parser when it is done writing to the RAM
Outputs:
addr: Requested data address in RAM
char_addr(7:0): Output code sent to char_rom.
Verification:
The correct behavior of the display module is directly represented on the VGA monitor. The output can be corroborated with the output from the scanning program that came included with the magnetic stripe reader.
clock_scale
This module accepts a 100 MHz clock signal and scales it to 50 MHz.
Inputs:
clk: 100 MHz clock signal
Outputs:
clock_50MHz: 50 MHz clock signal
Verification:
If erratic display behavior occurs, this module will be inspected.
ps2decode
This module grooms the output of ps2core since information is passed when a key is released.
Inputs:
hexcode(15:0): Data received from the ps2core module
Outputs:
char(7:0): Character data
Verification:
During one stage of the development, the output of the ps2decode module will be tied to the FPGA's LEDs and the last bit of transmission will be verified with the output from the scanning program that came included with the magnetic stripe reader.
parser
This module parses the stream of data from ps2decode and replaces formatting characters with spaces. The data is then stored sequentially in the RAM.
Inputs:
char(7:0): Data received from the ps2decode module
clk: Clock from the clock generation module
Outputs:
data(7:0): Data byte to be sent to the RAM to be displayed
addr: The address where the data will be put in the RAM
load: Controls the loading of data into the RAM
Verification:
During one stage of the development, the output of the parser module will be tied to the FPGA's LEDs and the last bit of transmission will be verified with the output from the scanning program that came included with the magnetic stripe reader.
RAM
This module stores 8-bit data.
Inputs:
clk: Clock from the clock generation module
data(7:0): Data received from the parser module
load: Controls the loading of data into memory
addr: Address where the data will be stored
sclr: Synchronous clear of the memory
Outputs:
dout(7:0): Outputs the data.
Verification:
The RAM module is a top level module for several memory sub-modules. If erratic program behavior occurs, this module will be verified for correct connections and logic.
Pre-existing Modules
char_rom
This ROM contains information about which pixel to display.
Inputs:
char_row(2:0): Row of the pixel within the tile to display
char_col(2:0): Column of the pixel within the tile to display
char_addr(7:0): The output code sent from the display module
Outputs:
out_pixel: Pixel on/off information
ps2core
This module formats the data input into the ASCII format.
Inputs:
ps2clk: 100 MHz clock signal (buffered from ps2c)
ps2data: The data sent in by the card reader (ps2d)
Outputs:
hexcode(15:0): Output to the parser module
vga_sync
This module computes pixel coordinates currently drawn and manages horizontal and vertical sync signals to VGA output. Also includes a video_on signal which should cause the RGB outputs to display black when low.
Inputs:
clock_50MHz: 50 MHz clock signal (converted to 25 MHz internally)
Outputs:
pixel_row(9:0): 10-bit value of currently drawn Y coordinate
pixel_column(9:0): 10-bit value of currently drawn X coordinate
h_sync: Horizontal sync for the VGA port
v_sync: Vertical sync for the VGA port
video_on: Asserted when the row and column outputs are valid
vga_buffer
If video_on is low, then pixel should be black (RBG = "000"). Otherwise it buffers the output to provide clean edges on the picture.
Inputs:
clk: 50 MHz clock signal
red_in: Red bit input
green_in: Green bit input
blue_in: Blue bit input
video_on: Asserted when pixel_row and pixel_column are valid
Outputs:
red_out: Red signal to VGA port
green_out: Green signal to VGA port
blue_out: Blue signal to VGA port
Expected Deliverables
Using the parts listed, we will construct a fully functional magnetic card reader and be able to display the information encoded on the card's stripe to the VGA monitor.
Phase 4
Review of Proposed Work
Overall, the project design has deviated slightly. After careful inspection, the project needed fewer modules for proper functioning, but module functionality has changed.
1. Module: parser. The signal processing module will groom and interpret the data and send it to a memory interface. Developer: Thomas Donaldson 2. Module: RAMB16_S9. A memory interface will store the card's information in the FPGA's Block RAM. 3. Module: display. A display module will display the contents of the memory to a VGA monitor. Developer: Eugene Sandberg 4. Module: mux2to1_11b. A two-to-one, 11-bit multiplexor. Developer: Thomas Donaldson
Schematic
Figure 1 - Top Level Schematic
Snapshots
Figure 2 - Snapshot of Deliverables
Verification Plan
To verify that the system is functioning, we connected the card reader to a windows based computer, opened up notepad, and streamed the data from a card into the window. These values become the expected values for testing the FPGA modules. After connecting all the modules and programming the FPGA, each card will be presented to the reader in turn, and the output will be compared to those obtained from notepad. The module will be considered functional if it is able to read and display the date of each card. During implementation we tied critical pins to leds to see if we were successfully switching states and transfering between modules.
Deliverables
Each time a card is swiped the encoded information will be displayed on the VGA monitor.
Project Changes
There were not much changes from the original design. We had to create a custom mux, as well as add the clk input to parser and the display. Also we had to change a few bit widths.
Project Files
The original, first-attempt at the card reader. This contains a robust, full-state parser and display module. This does not function properly, and caused us to develop the simplified projects below.
Turned in for the project deadline. It operates in a one-shot read, so only one card swipe is stored.
A fully stripped down version of the card reader. A very basic FSM in the parser module, and a direct feed from the RAM -> char_rom -> vga_buffer. This was for troubleshooting the various developed modules.
