ECE3714 Digital Devices

From Ece

Instructor: Jane Nicholson-Moorhead
Prerequisites: Credit or registration in CS 1213, CS 1233, or CS 1284
Office hours policy: MWF 11-12. Stop by during these office hours without an appointment. You can call or email for an appointment to make sure you can be seen.
Textbook: Fundamentals of Digital Logic with Verilog Design, Second Edition, Stephen Brown, Zvonko Vranesic
Meeting times: MWF 9:00-9:50AM (section 1), MWF 10-10:50AM (section 2) in Simrall 129

Lab: weekly in Simrall 308

ECE3714 Digital Devices and Logic Design is an undergraduate course in Electrical and Computer Engineering at Mississippi State University.

Course Description

MSU's Catalog Description

Digital Devices (Three hours lecture. Three hours laboratory.)
    Binary Codes, boolean algebra, K-Maps, combinational logic design, flip-flops, combinational building blocks, synchronous sequential logic design, sequential building blocks, programmable logic devices, MSI logic devices, adder circuits.

Objectives

Introduce students to the concepts of binary numbers, codes, and arithmetic. Introduce students to Boolean algebra and its applications. To develop the students ability to analyze and design combinational logic circuits. To develop the students ability to analyze and design sequential logic circuits and finite state machines. To introduce students to more complex logic circuits. To introduce students to computer-based digital design techniques.

Lab Problems / Solutions

Week 10 : Basic Sequential Logic Design

Working 7 segment display

Brief Xilinx HowTo

Adding a New Source

1. In an existing project, right click an empty space in the Sources box (This is in the upper left corner).
2. Click "Add New Source".
3. Choose the Source Type (usually Schematic or Testbench WaveForm for this class).
4. Name the source.
5. Click next, and then click finish.

Creating a Net Name

Creating a New Project

1. Open Xilinx Program Navigator.
2. Click File/New Project
3. Give the project a name.
4. Set the top-level source to schematic.
5. Click Next.
6. Ensure the first 3 options are as follows:

       Product Category:         General Purpose

       Family:                   CoolRunner XPLA3 CPLDs

       Device:                   XCR3064XL

7. Leave the other options as they are, and click next.
8. Click next twice, and then click finish.

Creating a Schematic Symbol

1. In an existing project, choose "Synthesis/Implementation" in the "Sources For" dropdown box.
2. Select the schematic you wish to make a symbol for by clicking it once.
3. In the "Processes" box, double click "Create Schematic Symbol" (This is under Design Utilities).

Creating a Testbench Waveform

1. Create a new source of type Testbench WaveForm (Make sure you select the correct schematic to associate the WaveForm with).
2. Choose the "Combinatorial (or Internal Clock)" button in the "Clock Information" box.
3. Click Finish.
4. Click the lines in the WaveForm that appears, and observe how the lines rise and fall.
5. Arrange the lines in such a fashion that all combinations of high and low lines are present.
6. Save the WaveForm.

Generating a Programming File

Selecting an Appropriate Clock Signal

Simulating a Circuit

1. Create a testbench waveform for the circuit.
2. On the "Sources For" dropdown list, select Behavioral Simulation.
3. Select the waveform you wish to simulate by clicking it once.
4. On the processes tab, double click Simulate Behavioral Model. (This is in the Xilinx ISE Simulator category)

Common Xilinx ISE Problems/Solutions

Before you even begin to search for an unusual problem, please note that software updates are the best method of solving bugs. Select Webupdate from the Help menu in Xilinx occasionally to check for these updates. Please note that since the beginning of the Fall Semester of 2007, Service Pack 3 has been released. This is a very important update as it fixes many bugs.

Installation Problems

Before you can download the software from Xilinx, you must create a username. Once you create the account however, there may be a problem with being able to download the software. If this occurs, restart your browser, and hopefully this fixes the problem.

Duplicate Net Names

Symptom(s)
While naming a wire or pin, an error is displayed.
Description
This problem is caused by the user attempting to assign a net name to a pin or a wire of the wrong polarity when a pin already has been assigned that net name.
Solution
Either choose a different net name for the current component.
OR
Rename the component that has been assigned the desired net name.

Failure to Include a Constraints File when Programming a Chip

Failure to Save Schematic

Failure to Save Testbench WaveForm

Inappropriate File Name/Directory Name

Symptom(s)
Description
This problem is caused by a user attempting to save a Xilinx file with a path name longer than 64 characters.
It is also caused by beginning a file name with a non-alphabetical character or including a space in a file name.
Solution
1. Choose a directory close to C:\ for your project folder.
2. Always begin a file name with a letter.
3. Never place spaces in a file name.
4. Make file names short.

Incorrect Polarity on an I/O pin

Unmatched LOC

Symptom(s)
Errors during translate step while implementing.
Description
This problem is caused by Xilinx attempting to assign constraints that are not used in your circuit.
Solution
1. Right click Implement Design in the processes tab.
2. Select Properties.
3. In the Fitting category, ensure that the "Allow Unmatched LOC Constraints" box is checked.
4. Click Apply, and then click OK.

Textbooks

• Chapters

1. Introduction
2. Number Systems and Codes
3. Digital Circuits
4. Combinational Logic Design Principles
5. Hardware Description Languages (HDLs)
6. Combinational Logic Design Practices
7. Sequential Design Principles
8. Sequential Logic Design Practices
9. Memory, CPLDS, and FPGAS

Links

ECE 3714 Homepage
ECE Submission Page