ECE4743 Digital Systems Design (Fall 2007)

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Class Time & Location

MWF 10:00-10:50am

Simrall 203

Instructor

Sherif Abdelwahed

Assistant Professor

Office Hours: MW 1:30-3:00pm or by appointment

Lab Instructor

Ridzky Riyadi

The Lab Policy is provided here.

Textbook

R. Reese, Introduction to Logic Synthesis Using Verilog HDL, Morgan & Claypool Publishers, 2006.

Class e-mail

ece4743@ece.msstate.edu

Grade Determination

Tests: 45%

Lab: 20%

Project: 10%

Final: 25%

Grading Scheme

A: 100-90

B: 89-80

C: 79-70

D: 69-60

F: 59-0

Attendance

Students are expected to be present for all tests and for the final exam. In extreme cases, I may arrange a make-up test. I will not be taking regular attendance, but I strongly suggest coming to class as the tests are based off of material discussed in class. It is the student's responsibility to contact me in advance to explain the situation and arrange an alternate plan.

Prerequisites

Digital Devices (ECE3714)

Lecture Slides

Tests

No calculators/PDAs/laptops/phones etc.
Write legibly
Make your final answers clear
Test 1 will be a take home exam
For Test 2-5 are closed book, closed notes.

Test 1: Wednesday, August 28. Due Friday August 31.

Test 2: Friday, September 14, 2007.

Test 3: Friday, October 5, 2007.

Test 4: Monday, October 22, 2007.

Test 5: Monday, November 12, 2007.

The first key to doing well on the tests is to study the old exams. There are many problems on them which I use for future exams with perhaps some small modifications. It is also excellent practice to work the problems. If you understand how to do the problems on the old exams, then you will be well prepared.

The second key to doing well on the exams is to prepare a good page of notes. Just by going through the process of looking up information on the slides, you come to understand what you know and what you don't know. The decision to put something on the exam requires a certain level of understanding of the material. It's also ok to put old exam problems and answers on there since I use a lot of old material; however, be sure you know how the problem works since I often slightly change old problems for new exams.

Handouts

Fall 2007 Syllabus and Class Policy

Academic Dishonesty

You may DISCUSS work, and verbally answer questions about lab work from other students. You may NOT SHOW your work to another student, or provide an 'old copy' as an example. Looking at or copying any material (schematics, VHDL files, simulation files, etc.) from another student is considered academic dishonesty. The person providing this material would also be guilty of academic dishonesty. If I find a student guilty of academic dishonesty, expect an F in the course and an academic dishonesty claim to go into your permanent academic record. For graduate students, an F in any course results in immediate expulsion. For more information see the school honor code

Software

We will be using a software package called Xilinx ISE WebPack for digital logic programming in this class. This is free software that can be downloaded from the Xilinx web page. For simulations, we will use the Modelsim software, which is also a free download from the Xilinx web page. We will discuss how to install and use the software in lab. The labs will be oriented around your laptops, so you will need to install the software yourself. You must have the software downloaded before coming to lab since it is a very large download (~850MB). Instructions for downloading it are included in lab 1. This software is also available on the workstations in the lab if you do not have a laptop. You can also use the Quick Start Tutorial to answer many questions about how to use the software, including HDL and schematic entry, simulation, constraints, implementing, and downloading.

Hardware

The labs this semester will require each student to purchase the Digilent, Inc. Basys development board. These cost $59 each and can be purchased directly from the Digilent, Inc. homepage. Included with each kit is a power supply and download cable. We decided to do this so each student can have hands-on experience with FPGA hardware. Each board has 8 LEDs, 8 switches, 4 push buttons, and a 4 digit numerical display. There are also connections for a VGA monitor and a PS/2 port for keyboards/mice. We will be using all of these in the lab.

We strongly recommend doing the labs on your laptops. If your laptops do not have a parallel port, then you won't be able to use the download cable. If you don't have a suitable laptop, some computers will be available in lab for development and programming.

Labs

The labs offered this semester will have different accomplishment levels. This is designed so each student can decide how many hours he/she wants to put into the lab. Each level carries a grade of A,B,C. The labs are designed so that completing the 'C' level work will lead directly into the 'B' level work, which will in turn lead into the 'A' level work. Graduate students must complete at least the 'B' level work. There are weekly quizes at the beginning of the lab period and a lab final during the last week of class. Be sure to bring your laptops to lab. If you do not have a laptop, then there are a few workstations that you can use.

If you use the Basys board, use the constraints file provided here. When you open the project in the lab files provided below you will have to change the FPGA for which it is synthsizing the design. Do this by right clicking on "xc3s200-4ft256" in the Sources window and select "Properties...". Change the Family to Spartan 3E, change the Device to XC3S100E, and change the Package to VQ100.

Lab Schedule
Lab 1	week of Aug 27	Software Installation and Tutorial
Lab 2	week of Sept 5	Combinational Verilog: Shift-Add-3
Lab 3	week of Sept 10	Sequential Verilog: Board Evaluation
Lab 4	week of Sept 17	Finite State Machines: Calculator
Lab 5	week of Sept 24	IP Cores: Pong
Lab 6	week of Oct 1	Memories: Raster vs. Tiles
Lab 7	week of Oct 8	Image Processing: Dithering and Strobing
Lab 8	week of Oct 15	LFSRs: Cryptology
Lab 9	week of Oct 22	Pulse Width Modulation: Faders
Lab 10	week of Oct 29	Embedded Processors: Picoblaze
Lab Final	Nov 14

Lab Tips

General:
- Be sure to include the constraints file in your project. If you're seeing strange things on the outputs, this may be the problem.
- If your code compiles, but doesn't do what you want it to: READ THE WARNINGS
  - The warnings are there to tell you that you probably made a mistake, but it will compile your code anyway
  - If it optomized something out, it will give you a warning - that's usually a mistake
  - It will tell you when it finds an asynchronous loop
  - It will tell you of unassigned I/O
Verilog code:
- Make simple always blocks
  - Only assign few related outputs
  - More smaller process statements are better than one big one
  - The compiler is not very smart
- Always be able to draw a block diagram of the circuit you are trying to describe
- Watch out for asynchronous loops in your code
  - Make sure you can't trace a combinational path
  - Temporary signals make this deceptive
Schematic Entry:
- Use the wire naming tool - don't double click on a wire to name it
- If you rename a wire, it will rename all of the wires of the same name

Projects

There will be a team project this semester lasting three weeks. The project will use the Pegasus development board. During the semester you will submit a proposal for their project, and it must be approved by the instructor. The project must have a high "wow" factor and be attractive. The project should be designed as if you trying to convince a high-school senior or freshman to enter the ECE department.

A detailed description and guidelines of the project

Phase 1 Due: Nov 2

Phase 2 Due: Nov 9

Phase 3 Due: Nov 16

Phase 4 Due: Nov 23

Demonstrations: Apr 28

4743 Project Template Page

Fall 2007

Team 1: creat page
- Venkata Nookala, Lakshmi Pragada, Venkata Puvadi
Team 2: creat page
- Frank Holland
Team 3: creat page
- Chris Dailey, Michael Weir
Team 4:creat page
- Charlie Mraz
Team 5: Asteroids
- Steven Austin, Jerome Walker
Team 6:creat page
- Andrew Thigpen, Joshua Wilson

Previous Projects

Spring 2007:

Team 1: Etch-A-Sketch
- T. Shannon, K. Bui, J. Brantley
Team 2: Kaboom
- P. Duckworth, C. Steiner, J. Ward
Team 3: Breakout
- J. Chae, J. Russell, K. Vu
Team 4: SSI System
- M. Elaprolu, D. Koneru, P. Karnati, A. Yerramreddy
Team 5: Collision Warning System
- R. Alapati, N. Puppala, B. Gokaraju

Fall 2006:

Team 1: USB Robot
- J. R. Sakalaukus, J.B. Lorens, J.A. Rapier, Y. Shimomoto
Team 2: Team MCR
- J. B. Leatherwood, J.A. Lasseigne, J. S. Wilson
Team 3: Pacman
- R. A. Riyadi, J. R. Bryant, N. H. Sephus, T. L. Porter
Team 4: Sound Recorder
- Rooban Venkatesh K.G.T, Y. Chen, B. L. V. Goli
Team 5:Motion Detector
- S. Koduri, M. Kaur, D. Segapalli
Team 6: FPGA cluster
- D. Godavarthi, R.D. Anderson, A. Perumalla

Spring 2006:

Team Elves: IP Cores Lab: The Baloon Hunt
Team PWM_Audiophiles: PWM Audio Player
Team XYZZY: FSM Lab: Maze
Team Wireless Pong: Wireless Pong

Fall 2005:

Team Syzygy: Computer Fan Control
Team Illumination Science: Light-Bright Toy
Team Snooze: Alarm Clock
Team NTN Design: PoV Game
Team Cyclotech: Cyclocomputer

Spring 2005:

Team Ramrod: Weather Station
Team 2: Pegasus Clock
Team CCA: CCA Tank Monitor
Team High Fidelity: Graphical Equalizer
Team H.A.L.: Sunlight Replicator

Reference Material

Web pages of interest

Bypass Capacitors
Transmission Lines
Wishbone Specifications Rev B.3
Gameboy/Xilinx Robots
Lego logic gates
Nintendo DS passthrough using Digilent Spartan3 board
Other Universities using FPGAs
- Digilent Pegasus boards
- Other Digilent boards
- Other Xilinx FPGAs
- Altera FPGAs
ASM web page references
- Concordia University

Data Sheets

PicoBlaze Processor
Altera Stratix FPGA
Altera Flex10K FPGA
Altera Max 7000A FPGA
Xilinx Virtex FPGA
Xilinx Spartan-II FPGA
Spartan-3 FPGA
- Block RAM note
Actel MXDS FPGA
Cypress Ultra37000 CPLD
Cypress PAL20 PLD
Cypress PAL22V10 PLD
Texas Instruments Logic Selection Guide: list/discussion all of the low voltage IO families

Sample Tests

Homework problems

Personal tools

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