ECE8990-07 High-speed Digital Systems Design
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Contents |
Class Time & Location
MWF 11:00-11:50am
Simrall 104
Instructor
Justin S. Davis, Ph.D.
Assistant Professor
Office Hours: MW 1:30-3:00pm or by appointment
Textbook
J. Davis, High-speed Digital Systems Design, San Rafael, CA: Morgan & Claypool Publishers, 2006.
Optional Reading:
H. Johnson, High-speed Signal Propagation: Advanced Black Magic, Prentice Hall, 2003.
Class e-mail
TBA
Grade Determination
Tests: 50%
Projects: 25%
Final: 25%
Grading Scheme
A: 100-90
B: 89-80
C: 79-70
D: 69-60
F: 59-0
Test Schedule
Test #1: Sept 25 (Monday)
Test #2: Oct 20 (Friday)
Test #3: Nov 20 (Monday)
Final: Dec 7 (Thursday) 3:00-6:00pm
Projects
The projects this semester will be done outside of class. I recommend using your personal computer, but the computer labs can be used as an alternative. I will assign teams for any team projects. You should start on the the project immediately when they are assigned since they generally take longer than you plan for.
Bypass Capacitor Array
- Design a power distribution system similar to the example in the book.
- Include two graphs of impedance vs. frequency of the bypass capacitor array
- First graph should have four plots
- Only one 470uF capacitor
- All bypass capacitors
- Bypass capacitors & via inductance
- Bypass capacitors & via inductance & embedded capacitance
- Second graph should have one plot for every capacitor value
- Each plot should contain all the capacitors of that value
- First graph should have four plots
Wiki Links
- Web Content Assignment: Due Oct 9th.
- Add 5 external links to the above schedule for the topic covered so far.
- Be sure to log in when making edits.
- Include your name at the end of each link.
Attendance
Students are expected to be present for all tests and for the final exam. In extreme cases, I may arrange a make-up test. I will not be taking regular attendance, but I strongly suggest coming to class as the tests are based off of material discussed in class. It is the student's responsibility to contact me in advance to explain the situation and arrange an alternate plan.
Academic Dishonesty
You may discuss work, and verbally answer questions about work from other students. You may not show your work to another student or provide an old copy as an example. Looking at or copying any material (schematics, HDL files, simulation files, scope plots, etc.) from another student is considered academic dishonesty. The person providing this material would also be guild of academic dishonesty. If I find a student guilty of academic dishonesty, expect an F in the course and an academic dishonesty claim to go into your permanent academic record. For graduate students, an F in any course results in immediate expulsion.
Schedule
August 18: Introduction
August 21-25: Power Systems, Bypass Capacitor Array Design & Simulation
Seattle Robotics Society: The Basics: Bypass Capacitors (Davis)
signal consulting inc.: Bypass Capacitor Layout (Huang)
Capacitor Design Data, Decoupling Placement, How-To (Huang)
Power-integrity and ground-bounce simulation of high-speed pc boards (Saurage)
Proper use of bypass capacitors to improve overall power supply integrity(Fatima)
Bypass Capacitors in High Speed Environment(Fatima)
Power Supply Bypassing (Fatima)
Bypass Capacitor & Simulation(Fatima)
High-End Digital Systems Give Thumbs Down to Rules of Thumb (Taylor)
August 28-September 1: Layer Stacking, Embedded Capacitance, Via Modeling
Layer Stacking Guidelines (Huang)
PCB Impedance and Capacitance Calculator (Huang)
Effects of Vias on PCB Traces (Huang)
High Frequency Equivalent Circuit Model of Vias (Saurage)
Layer Stacking-Four Layer Board(Fatima)
Layer Stacking-Six Layer Board(Fatima)
Layer Stacking-Eight Layer Board(Fatima)
Embedded PCB Capacitance(Fatima)
Power/Ground Via distribution (Fatima)
Blind Via Capacitance (Fatima)
Simulation and Analysis of Via Effects on High-Speed Signal Transmission on PCB (Hathcock)
Splitting Planes For Speed and Power (Taylor)
Layout of Mix-Signal PCBs (Taylor)
Trace Width Calculator (Taylor)
September 6-8: Ideal Transmission Lines, Characteristic Impedance, Propogation Velocity
Transmission Line Characteristic Impedance (Young)
Microstrip Transmission Line Characteristic Impedance Calculator (Young)
Velocity of Propagation in Tranmission Lines (Saurage)
PCB Trace Impedance Calculator (Hathcock)
Transmission Line Characteristic Impedance (Fatima)
September 11-15:
Ideal Transmission Lines, Reflections, Terminations
Ideal Transmission Lines (Saurage)
Reflections on Transmission Line (Fatima)
Standing waves/Reflections in a Transmission Line (Fatima)
Transmission Line Terminations (Fatima)
Transmission Lines- Overview (Fatima)
Termination and Reflections in a Transmission Line (Fatima)
Guidelines for Designing High-Speed FPGA PCBs (Hathcock)
September 18-22: Ideal Transmission Lines, Bounce Diagrams
Java Bounce Simulator (Saurage)
Heriot-Watt University: Interactive Bounce Diagram (Young)
Creating a Bounce Diagram (PDF) (Young)
Bounce Diagram -Graphical Presentation (Fatima)
Lossless Transmission Line (Fatima)
September 25-29: Lumped Element Model, RC Model, LC Model
October 4-6: Skin Effect, Proximity Effect, Surface Roughness
Modeling Skin Effect in Spice (Saurage)
October 9-13: Dielectric Effect
October 16-20: Crosstalk
October 23-27:
October 30-November 3: Simulation Tools
November 6-10: Clock Recovery, Jitter
November 13-17: Bit Error Rate
November 20: Test, Holiday
November 27-December 1: Review
Extra Credit / Make up points
Bonus points for Test 1: Make up Test
Due Friday Oct 6th at 10am - either hand in or email it.
Useful Web links
