FPGA cluster

From Ece

Team Cluster

Our goal is to make a video game playing, image processing FPGA clustered system.

Team Members

D. Godavarthi -- checker

A. Perumalla -- recorder

R. Anderson -- coordinator

Phase 1

Introduction

In past laboratory assignments we have implemented hardware designs that explored the image processing abilities of the Digilent Inc. Spartan III starter board. Some implementations include image rendering and a classic video game. However, they are stand-alone designs targeted for a single board and display. What if we wanted to execute multiple imaging tasks at once? Do we implement a large design and hope it fits on a single FPGA or have several of them perform a different task in parallel? We choose the latter?

Concept

Developing a image processing system using FPGA clustering technique. Multiple image rendering processes can be executed simultaneously on individual FPGAs then assembled into a single display using a data managing controller FPGA. FPGA-to-FPGA data transfers are handled through a wired interconnect and received by the controller.

Proposed Work

1. A three FPGA cluster will be implemented using Spartan III starter boards.
2. Two FPGAs, f1 and f2, will be responsible for the image processing/rendering with one implementing a video game and the other generating an image of choice.
3. The game FPGA will support a keyboard input for user game play.
4. Both processing FPGAs will serially deliver their data to the third FPGA; data will be "pushed" to it.
5. The third FPGA (f3) will serve as a data managing controller and image display device.
6. During execution, f3 will receive the serially delivered data, store it, and prepare the data for a VGA display; clock synchronization will have to be considered for data reception.
7. ALL three FPGAs are interconnected using a wiring technique and the expansion slots of the starter boards.

Required Parts

• 3 Spartan III starter boards
• Connecting Wires
• VGA monitor
• PS/2 keyboard
• coffee
• donuts

Expected Deliverables

We will use the keyboard to play the game. The game FPGA should receive this input and adjust accordingly. The image FPGA should render the image with the appropriate colors and resolution. The controller should be able to buffer the date pushed to it, process it, and display it to screen.

Phase 2

Introduction

In past laboratory assignments we have implemented hardware designs that explored the image processing abilities of the Digilent Inc. Spartan III starter board. Some implementations include image rendering and a classic video game. However, they are stand-alone designs targeted for a single board and display. What if we wanted to execute multiple imaging tasks at once? Do we implement a large design and hope it fits on a single FPGA or have several of them perform a different task in parallel? We choose the latter?

Concept

Developing a image processing system using FPGA clustering technique. Multiple image rendering processes can be executed simultaneously on individual FPGAs then assembled into a single display using a data managing controller FPGA. FPGA-to-FPGA data transfers are handled through a wired interconnect and received by the controller.

Proposed Work

1. A three FPGA cluster will be implemented using Spartan III starter boards.
2. Two FPGAs, f1 and f2, will be responsible for the image processing/rendering with one implementing a video game and the other generating an image of choice.
3. The game FPGA will support a keyboard input for user game play.
4. Both processing FPGAs will serially deliver their data to the third FPGA; data will be "pushed" to it.
5. The third FPGA (f3) will serve as a data managing controller and image display device.
6. During execution, f3 will receive the serially delivered data, store it, and prepare the data for a VGA display; clock synchronization will have to be considered for data reception.
7. ALL three FPGAs are interconnected using a wiring technique and the expansion slots of the starter boards.

Modules

• FPGA1
  • Implements a video game
• FPGA2
  • Used for image processing
• FPGA3
  • FIFO1(8 registers of 8 bit length)
  • FIFO2(8 registers of 8 bit length)
  • Finite State machine
  • Draw_vga
  • It is the top-level module/FPGA

Required Parts

• 3 Spartan III starter boards
• Connecting Wires
• VGA monitor
• PS/2 keyboard
• coffee
• donuts

Expected Deliverables

We will use the keyboard to play the game. The game FPGA should receive this input and adjust accordingly. The image FPGA should render the image with the appropriate colors and resolution. The controller should be able to buffer the date pushed to it, process it, and display it to screen.

Phase 3

Introduction

With a few modifications to our original design, we are still moving forward. The FIFO-base controller design has been changed to RAM-based design, which required more information (address, enable bits) to be passed from FPGA-to-FPGA in parallel. We also discovered the advantages of using the RAM but had to consider available FPGA resources as well.

Concept

Since we are working with three different clock domains, we face a problem with the phase synchronization. We decided to use two Xilinx core generated dual-ported RAMs to solve the synchronization problem. We are aware that other more efficient synchronization techniques could be implemented. However, time and other demands (tests, projects, classes) limited our progress. Therefore, we settled for the least time consuming method.

The RAM is used to store in-coming data temporarily so that to allow the control FPGA to display an image on the monitor with limited loss of data (pixels). The RAMs are dual ported, thus writing to the RAM will be controlled by the clock and write-enable (WEB) signal from the image rendering FPGAs. A read is controlled by the display/control FPGA clock and employs a read after write to avoid reading incorrect data. Addresses, pixel colors, WEB, clock, and other signals are sent in parallel to the control FPGA where the pixel colors are written to memory. The control FPGA reads from both memories and displays the output on screen. Memory outputs are multiplexed to allow the correct image to be displayed at its proper on-screen location. Image resolutions are scaled so that multiple images could be shown at once.

Proposed Work

1. A three FPGA cluster will be implemented using Spartan III starter boards.
2. Two FPGAs, f1 and f2, will be responsible for the image processing/rendering with one implementing a video game and the other generating an image of choice.
3. The game FPGA will support a keyboard input for user game play.
4. Both processing FPGAs will serially deliver several data bits in parallel to the third FPGA; the data is "pushed".
5. The third FPGA (f3) will serve as a data managing controller and image display device.
6. ALL three FPGAs are interconnected using a wiring technique.

Modules

• FPGA1
  • 15-bit address generator
  • Implements a video game (a shooter)
  • Sends data from A2 to the A2 expansion slot of FPGA3
• FPGA2
  • 14-bit address generator
  • Renders the snoopy image from a previous lab
  • Sends data from A2 to the B1 expansion slot of FPGA3
• FPGA3
  • 20-bit address generator
    • Uses same addressing scheme as FPGAs 1 and 2
    • 15 LSBs used for game RAM address
    • 14 LSBs used for image RAM address
  • one 15-bit dual port RAM1 for game
  • one 14-bit dual port RAM2 for snoopy
  • 2-input MUX
  • Draw display
  • It is the top-level module/FPGA

Required Parts

• 3 Spartan III starter boards
• Connecting Wires
• VGA monitor
• PS/2 keyboard
• bells
• whistles

Expected Deliverables

We will use the keyboard to play the game. The game FPGA should receive this input and adjust accordingly. The image FPGA should render the image with the appropriate colors and resolution. The game or image data should be received by the controller and written to memory using the external clock of the sending FPGA. The controller FPGA will generate an address using the same addressing scheme as the rendering FPGAs then use that address to read data from the RAM. The read process should run in step with the controller FPGA's clock. A modified VGA-synch module, borrowed from previous labs, will not only control the horizontal and vertical synch, but also select which RAM output to display on screen and its location. RAM output will go to a MUX where the VGA-synch module will select which output to drawn. The selected output will traverse the MUX into our draw display module and onto the monitor screen.