JSR

From Ece

Team Members

• Sam Shannon
• Richard Corey
• Jaron Martin

Design Overview

Our design consists of 16 instructions and 16 registers, both of which are indexed using a 4-bit wide address. Our instruction format is 16-bit with the 4-bit opcode contained within. This is in keeping with guidelines set in the class project, as opposed to the more standard 32-bit addressing scheme used in many modern processors.

Our architecture consists of an additional instruction format, I-Long. This increases the range of immediate values from 4 bits to 8 bits as opposed to the I-Format and its instruction format is described below.

Instruction Format

R-Format

I-Format

I-Long Format

J-Format

Instruction Set

Assembly Language Code

   # addi $v0 $zero 64   # $v0 = 0040hex;.
   add $v0 $zero $zero
   pe $v0 64
   lui  $v1 16         # $v1 = 1010hex;
   # addi $v1 $v1 16
   add $v1 $zero $zero
   pe $v1 16
   #addi $v2 $zero 15   # $v2 = 000Fhex;
   add $v2 $zero $zero
   pe  $v2 15
   # addi $v3 $zero 240  # $v3 = 00F0hex;
   add $v3 $zero $zero
   peu $v3 240
   add  $t0 $zero $zero # $t0 = 0000hex;
   # addi $a0 $zero 16   # $a0 = 0010hex;
   add $a0 $zero $zero
   pe  $a0 16
   addi $a1 $zero 5    # $a1 = 0005hex;
   
   #Temporary registers to store values for comparisons and assignments
   lui  $t2 1          # Compare Val for: if ($t0 > 0100hex) then {
   lui  $t3 255        # Store val for: Mem[$a0] = FF00hex;
   # addi $t4 255        # Store val for: Mem[$a0] = 00FFhex;
   addi $t4 $zero $zero
   peu $t4 255

checkLoop:

   ble  $a1 $zero exitWhileShort
   nop
   j beginWhile
   nop

exitWhileShort:

   j exitWhile
   nop

beginWhile:

   addi $a1 $ai -1     # $a1 = $a1 - 1;
   lw   $t0 0($a0)     # $t0 = Mem[$a0];
   ble  $t0 $t2 beginElse  # if ($t0 > 0100hex)
   nop    
   asr  $v0 $v0 3      # $v0 = $v0 / 8;
   or   $v1 $v1 $v0    # $v1 = $v1 | $v0;
   sw   $t3 0($a0)     # Mem[$a0] = FF00hex;
   j    skipElse
   nop

beginElse:

   sll  $v2 $v2 2      # $v2 = $v2 * 4;
   xor  $v3 $v3 $v2    # $v3 = $v3 xor $v2;
   sw   $t4 0($a0)     # Mem[$a0] = 00FFhex;

skipElse:

   addi $a0 $a0 2      # $a0 = $a0 + 2;
   j    checkLoop
   nop

exitWhile:

Machine Language Code

Responsibilities

Meetings

Progress

Divided the project by stages, begun individual work on each stage.

4/11/2011

• Finished Control Unit Module Table
• Finished Control Unit
• Finished Forwarding Module
• Further progress on individual stages