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Powerthirst - Ece
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Powerthirst

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Contents

  • 1 Team Members
  • 2 Design Overview
  • 3 Instruction Formats
    • 3.1 R Format
    • 3.2 I Format
    • 3.3 ADDI Format
    • 3.4 J Format
  • 4 Instruction Set
  • 5 Datapath
    • 5.1 Datapath without hazard detection
    • 5.2 Datapath with ADDI
  • 6 Project Files

Team Members

Team Leader: Ryan Storment
Team Member: Ivan Akimov

Design Overview

Most modern processors must support object-oriented programming efficiently, as many single-purpose devices are used as platforms for Java or C/C++, in which procedures and methods are called often (and recursively) in the code. For this reason, our instruction set will be designed to enhance the branching capabilities of MIPS. This will be done by providing several branching instructions, along with a dedicated "status" register in which each bit will represent some meta-data about the previously executed instruction, much like the architecture of the PIC family of processors. Register $t9 will be renamed $status for this purpose, and will not be user-modifiable. In addition, we will assume a falling-edge triggered configuration, in order to avoid the line interference caused by the pull-downs on a rising-edge configuration. This does, however, increase clock propagation time because of the combinational logic necessary to invert the signal.

Instruction Formats

In addition to the R, I, and J formats, a fourth format called ADDI was created to facilite larger unsigned integers to be used as arguments to the addi and subi instructions. This will allow values between 0 and 29-1, or 512 different values, up to 0x01FF to be specified.

R Format

Opcode Rs Rt Rd Func
4 bits 3 bits 3 bits 3 bits 3 bits

I Format

Opcode Rs Rt Immediate
4 bits 3 bits 3 bits 6 bits

ADDI Format

Opcode Rs Immediate
4 bits 3 bits 9 bits

J Format

Opcode Address
4 bits 12 bits

Instruction Set

NameMnemOperation OpcodeFuncFormat
AndandAnd $s1,$s2,$s3;
$s1 = $s2&$s3
0000
(ALUop)
000R
OrorOr $s1,$s2,$s3;
$s1 = $s2 | $s3
001R
AddaddAdd $s1,$s2,$s3;
$s1 = $s2+$s3
010R
SubtractsubSub $s1,$s2,$s3;
$s1 = $s2-$s3
011R
Exclusive OrxorXor $s1, $s2, $s3;
$s1 = $s2⊕$s3
100R
NorNornor $s1, $s2, $s3;
$s1 = $s2 $s3
101R
Add ImmediateaddiAddi $s1, 100;
$s1 = $s1+100
0001xxxADDI
Subtract ImmediatesubiSubi $s1, 100;
$s1 = $s1-100
0010xxxADDI
Shift Leftsllsll $s1,$s2,L;
$s1 = $s2<<L
0011xxxI
Shift Rightsrlsrl $s1,$s2,L;
$s1 = $s2>>L
0100xxxI
Or ImmediateoriOri $s1,$s2,100;
$s1 = $s2 | 100
0101xxxI
And ImmediateandiAndi $s1,$s2,100;
$s1 = $s2 & 100
0110xxxI
Branch if equalbeqBeq $s1,$s2,25;
if($s1==$s2) go to PC + 2 + 100
0111xxxI
Branch if greater thanbgtBgt $s1, $s2, L;
if ($s1 > $s2) goto L
1000xxxI
Branch if less than or equal toblteBlte $s1, $s2, L;
if ($s1 <= $s2) goto L
1001xxxI
Branch if not equal tobneBgt $s1, $s2, L;
if ($s1 != $s2) goto L
1010xxxI
Branch if last result zerobzBz L;
if (~$status[ZERO]) goto L
1011xxxJ
Branch if last result not zerobnzBnz L;
if ($status[ZERO]) goto L
1100xxxJ
JumpjJ 2500;
go to 5000
1101xxxJ
Load wordlwlw $s1,100($s2);
$s1=Memory[$s2 + 100]
1110xxxI
Store wordswsw $s1,100($s2);
Memory[$s2 + 100]=$s1
1111xxxI


Datapath

Datapath without hazard detection
This represents the pipelined datapath before hazard detection, much as depicted in the book. The main difference is the use of $status[ZERO] rather than a direct line, in order to select PCsrc. This method will be used to optimize branching instructions.
Datapath without hazard detection
Datapath without hazard detection
Datapath with ADDI
This represents the pipelined datapath with support for the ADDI-format instructions
Datapath with support for ADDI format
Datapath with support for ADDI format

Project Files

  • Project Proposal (corrected)
  • registerFile.h: Register file class
  • memory.h: Memory class
  • datapath.h: Datapath class
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