RFID reader
From Ece
Contents |
Phase 1 (Updated for Phase 2)
Objective
Our goal is to create an RFID reader capable of reading a 125 kHz RFID tag and displaying the card's unique 32-bit identification number on the seven segment display.
Team Members
Christopher Dailey – Recorder, Checker
Michael Weir – Coordinator, Checker
Concept
A RFID reader will be used in conjunction with the spartan board to output the contents of a RFID tag. When a RFID tag is placed in proximity of the of the reader’s antenna, the chip will excite the RFID tag, receive its contents, and send the data to the FPGA. The data must then be parsed and then on the seven segment display of the Spartan Board.
Required Parts
Spartan-3E Development Board
Datasheets: Reference Manuel, Schematics
ID Innovations ID-12 RFID Reader
Part Number: SEN-08419
Package: 11 Pin, 5 VDC
Unit Price: $29.95
Available: www.sparkfun.com
Delivered: 11/7/2007
125 kHz RFID Tags x3
Available: www.sparkfun.com
Delivered: 11/7/2007
Proposed Work
1. Christopher will develop a module that will interface with the RFID reader and receive the input data. 2. Michael will develop a module that will parses the input data and formats it to be displayed on the display. 3. Michael will develop a register bank module that will store the data for output.
Figure 1 - Modules used for RFID Reader
Modules
RFID Reader
This module handles the communication and input data coming from the RFID reader. Whenever this module receives a valid byte of data, it holds the load line to the Parser high for a clock cycle and outputs the byte.
Inputs:
Clock: 100 Mhz clock signal
RFID_IN: RS232 serial data input from the RFID chip.
Outputs:
Load: Signals Parser when next byte is ready to load.
Dout: Outputs byte of data to the Parser.
Verification:
Setup: The RFID reader will be connected to the the JA1 port of the Spartan board. Port JA1 is
connected to the RFID_IN pin of the module. For testing, the outputs Dout and Load will
be connected to a bank of 8-bit registers through a multiplexer.
Test: When a card is scanned, data will be streamed over the port. Each time the Load line goes
high, the select line will be incremented, changeing the destination register. The
switches on the board will then be used to determine which registers are diplayed to the
seven segment display. This will verify that all data is recieved from the chip.
Parser
This module determines which bytes of the data from the RFID Reader should be sent to the seven segment display as an output.
Inputs:
Din: Data received from the RFID Reader Module.
Load: Load enable. Tells the Parser when data is ready to be accepted.
Clk: Clock from the clock generation module
Outputs:
Dout: Data byte to be sent to the register bank to be displayed.
Write: Tells the register bank to write the data byte.
Select: Identifies which register in the bank to store the byte in.
formatError: Set high when the data is not formatted correctly.
CRCError: Set high when the calculated CRC value does not equal the sent CRC value.
Verification:
Setup: Connect DIN to the 8 switches of the Spartan Board. Connect Load to button 0 of the parser board.
Connect Dout to the tested register bank Din. Connect the Write to the tested register bank Load
pin. Connect the Select pins to the tested register bank select pins.
Test: The module will be tested with the following test vector: {0x02, 10 bytes of ASCII text, 2 ASCII bytes (CRC Value),
carriage return, line feed, 0x03}. The 8 switches will represent the appropriate byte. Pushing
button one will load the byte into the parser module. After the entire test vector has been loaded,
the seven segment display should display the 32 bit number that was sent to it by the RFID reader.
Register Bank
This module contains four 8-bit registers to store the output data.
Inputs:
Clk: Clock from the clock generation module
Din: Data received from the Parser.
Write: Write enable line for the registers.
Select: Identifies which register to write the data input to.
Outputs:
Dout1: Outputs the 2 most significant bytes of the output data.
Dout0: Outputs the 2 least significant bytes of the output data.
Verification:
Setup: Connect the eight bit Din input to the 8 switches of the Spartan board. Connect the Write enable
pin to button 0. Connect the Clk input to the clk of the Spartan board. Connect the Select bits to
the output of a 2 bit counter. Connect button 1 to the enable of the counter. Connect Dout1 and
Dout2 to a two to one multiplexer with the select line connected to button 2 and the output of the
multiplexer connected to the seven segment display.
Test: When button 0 is pushed the the byte represensted by the switches should be loaded into the
Register Bank. The corresponding seven segment display should show the new byte information.
Pushing button 1 will change the input select lines in the following pattern {00, 01, 10, 11}.
Pushing and holding button 2 will display the most significant word of the register bank. The
circuit will be tested to ensure that the correct byte is loaded in the correct register.
Pre-existing Module
Segdecoder
This module formats the data input into the format accepted by the seven segment display on the Baysis board.
Inputs:
Clk: 100 MHz clock signal
Char3: Most significant byte of the most significant character
Char2: Least significant byte of the most significant character
Char1: Most significant byte of the least significant character
Char0: Least significant byte of the least significant character
Outputs:
An: Output to the anode controller.
Ssg: Output to the seven segment display.
Expected Deliverables
When a RFID card is presented to the reader, the 32-bit identification number will be saved in the onboard registers. This value will then be displayed 16-bits at a time on the seven segment display. Switch zero will be used to select either the 16 most significant or 16 least significant bits.
Phase 3
Review of Proposed Work
1. A module to recieve and store data from the RFID reader. Developer: Christopher Dailey
2. A module that parces the recieved data and formats it for display on the seven segment display. Developer: Michael Weir
3. A register bank that will store the data for output and select the displayed bits. Developer: Michael Weir
Module Descriptions
RFID Reader
Figure 2 - RFID Module
Sub-modules (RFIDreader.v, Bdclkgen):
Bdclkgen.v: This module takes in the system clock and divides it down to generate a clock signal that matches the incoming data's baud rate. The RFID chip used outputs data at a baud rate of 9600, so a 9.6kHz clock signal is needed to recieve that data.
RFIDreader.v: This module recieves and stores the data from the RFID Reader, then passes the data on to the Parser. The module will oversample the input line while it is waiting for data. After recieveing the start bit, the data line is sampled using the clock provided by the Bdclkgen module. The data is stored in a shift regester as it arrives. Once a byte of data is recieved it will be sent to the parcer module.
Inputs:
Clock: 100 Mhz clock signal
RFID_IN: RS232 serial data input from the RFID chip.
Outputs:
Load: Signals Parser when next byte is ready to load.
Dout: Outputs byte of data to the Parser.
Parser
Figure 3 - Parser Module
This module determines which bytes of the data from the RFID Reader should be sent to the seven segment display as an output.
Inputs:
Din: Data received from the RFID Reader Module.
Load: Load enable. Tells the Parser when data is ready to be accepted.
Clk: Clock from clock generation module.
Outputs:
Dout: Data byte to be sent to the register bank to be displayed.
Write: Tells the register bank to write the data byte.
Select: Identifies which register in the bank to store the byte in.
state: Debug information to show the current state of the internal Finite State Machine.
counter: Debug information to show the current counter value. Counter is used by the Finite State Machine to determine when to change
states.
formatError: Set high when the data is not formatted correctly.
CRCError: Set high when the calculated CRC value does not equal the sent CRC value.
Register Bank
Figure 4 - Register Bank Module
Inputs:
Clk: Clock from clock generation module
Din: Data received from the Parser.
Write: Write enable line for the registers.
Select: Identifies which register to write the data input to.
Outputs:
HighWord: Outputs the 2 most significant bytes of the output data.
LowWord: Outputs the 2 least significant bytes of the output data.
Expected Deliverables
The expected deliverabes have not changed. When a RFID card is presented to the reader, the 32-bit identification number will be saved in the onboard registers. This value will then be displayed 16-bits at a time on the seven segment display. Button zero will be used to select either the 16 most significant or 16 least significant bits.
Phase 4
Review of Proposed Work
After completing the individual modules, they were connected to form the final design. Figure 5 shows the final schematic. After debugging the timing between the modules, 32-bit values were displayed on the seven-segment display. To verify that these values were correct, the reader was connected to hyperteminal. The ASCII values on the serial interface were compared to the values seen on the seven-segment display. This test confirmed that the circuit was outputing the correct ID number for each card.
Schematic
Figure 5 - Complete Schematic
Snapshots
Figure 6 - Physical Circuit Displaying lower 16-bits
Figure 7 - Physical Circuit Displaying higher 16-bits
Figure 8 - ID-12 Breakout Board
Verification Plan
To verify that the system is functioning, the 32-bit ID numbers from each card were obtained by using hyperterminal and the RFID reader chip. These values become the expected values for testing the FPGA modules. After connecting all the modules and programming the FPGA, each card will be presented to the reader in turn, and the output will be compared to those obtained from hyperterminal. The module will be considered functional if it is able to read and display the ID number of each card.
Deliverables
When a RFID card is presented to the reader, the 32-bit identification number will be saved in the onboard registers. This value will then be displayed 16-bits at a time on the seven segment display. Button zero is used to select either the 16 most significant or 16 least significant bits.
Project Changes
There were not many changes from the orignal plan. The Baud rate generator was made as a seperate module instead of being a sub-module of the RFID interface to allow easier integration with the other modules.
