RISCy Business

From Ece

Team RISCy Business is an ECE4713 Computer Architecture project team consisting of Jeff Brantley and Thomas Donaldson. RISCy Business has produced a partial CPU implementation based on the MIPS architecture in the course textbook.

Overview

Instruction Formats

R-Format:

Opcode	rs	rt	rd	func
4 bits	3 bits	3 bits	3 bits	3 bits

I-Format:

Opcode	rs	rt	immediate / address
4 bits	3 bits	3 bits	6 bits

LI-Format:

Opcode	rs	-	long immediate
4 bits	3 bits	1 bit	8 bits

J-Format:

Opcode	address
4 bits	12 bits

Register File

$v0	$v1	$v2	$v3	$a0	$a1	$t0	$t1
$0	$1	$2	$3	$4	$5	$6	$7

Instruction Set Summary

Name	Mnemonic	Operation	Note	Opcode	Funct	Format
Add	add	R[rd] = R[rs] + R[rt]		1111	0	R
Subtract	sub	R[rd] = R[rs] + R[rt]		1111	1	R
Set Less Than	slt	R[rd] = (R[rs] < R[rt]) ? 1 : 0		1111	10	R
Set Less Than Unsigned	sltu	R[rd] = (R[rs] < R[rt]) ? 1 : 0	(1)	1111	11	R
Or	or	R[rt]		1111	100	R
And	and	R[rd] = R[rs] & R[rt]		1111	101	R
Nor	nor	R[rt])		1111	110	R
Exclusive Or	xor	R[rd] = R[rs] ⊕ R[rt]		1111	111	R
Shift Left Logical	sll	R[rs] = R[rt] << ZeroExtImm	(2)	0001	—	I
Shift Right Logical	srl	R[rs] = R[rt] >> ZeroExtImm	(2)	0010	—	I
Shift Right Arithmetic	sra	R[rs] = R[rt] >>> ZeroExtImm	(2)	0011	—	I
Add Immediate	addi	R[rs] = R[rt] + SignExtImm	(3)	0100	—	I
Load Word	lw	R[rs] = M[R[rt]+SignExtImm]	(3)	0101	—	I
Store Word	sw	M[R[rt]+SignExtImm] = R[rs]	(3)	0110	—	I
Store Byte	sb	M[R[rt]+SignExtImm](7:0) = R[rs](7:0)	(3)	0111	—	I
Load Lower Immediate	lli	R[rs] = {8’b0, long immediate}		1000	—	LI
Load Upper Immediate	lui	R[rs] = {long immediate, R[rs](7:0)}		1001	—	LI
Branch If Equal To Zero	bz	if(R[rs]==0) PC=PC+2+BranchAddr	(4)	1010	—	I
Jump	j	PC=JumpAddr	(5)	1011	—	J
Bit Set	bset	(1’b1 << ZeroExtImm)	(2)	1100	—	I
Bit Clear	bclr	R[rs] = R[rt] & ~(1’b1 << ZeroExtImm)	(2)	1101	—	I
Bit Test	btst	R[rs] = (R[rt] & (1’b1 << ZeroExtImm)) != 0 ? 1 : 0	(2)	1110	—	I
No Operation	nop			0000	—	—

(1) Operands considered unsigned numbers (vs. 2’s comp.)
(2) ZeroExtImm = { 10{1b’0}, immediate }
(3) SignExtImm = { 10{immediate[5]}, immediate }
(4) BranchAddr = { 2{immediate[5]}, immediate, 1’b0 }
(5) JumpAddr = { address(7:0), 1’b0 }

Test Program

                             |  $v0 = 0040hex;	// initialized values
                             |  $v1 = 1010hex;
                             |  $v2 = 000Fhex;
                             |  $v3 = 00F0hex;
                             |  $t0 = 0000hex;
                             |  $a0 = 0010hex;
                             |  $a1 = 0005hex;
                             |
Loop:    lli $t0, 0          |  while ($a1 > 0) do {
         slt $t0, $t0, $a1   |
         bz $t0, EndLoop     |
         nop                 |
         nop                 |
         nop                 |
         addi $a1, $a1, -1   |      $a1 = $a1 –1;
         lw $t0, 0($a0)      |      $t0 = Mem[$a0];
         lli $t1, 0x00       |      if ($t0 > 0100hex) then {
         lui $t1, 0x01       |
         slt $t0, $t1, $t0   |
         bz $t0, Else        |
         nop                 |
         nop                 |
         nop                 |
         sra $v0, $v0, 3     |          $v0 = $v0 ÷ 8;
         or $v1, $v1, $v0    |          $v1 = $v1 | $v0; //or
         lli $t0, 0x00       |          Mem[$a0] = FF00hex;
         lui $t0, 0xFF       |
         sw $t0, 0($a0)      |
         j EndIf             |
         nop                 |
         nop                 |
         nop                 |
                             |      } else {
Else:    sll $v2, $v2, 2     |          $v2 = $v2 × 4;
         xor $v3, $v3, $v2   |          $v3 = $v3 ⊕ $v2; //xor
         lli $t0, 0xFF       |          Mem[$a0] = 00FFhex;
         sw $t0, 0($a0)      |
                             |      }
EndIf:   addi $a0, $a0, 2    |      $a0 = $a0 + 2;
         j Loop              |  }
         nop                 |
         nop                 |
         nop                 |
EndLoop:                     |  return;

;-------------------------------------------------
; Begin additional test for remaining instructions
;-------------------------------------------------

         add $v1, $v1, $v0   |  $v1 = $v1 + $v0;
         sub $v0, $a0, $v1   |  $v0 = $a0 - $v1;
         and $a1, $v1, $a0   |  $a1 = $v1 & $a0;
         nor $t0, $t1, $a1   |  $t0 = ~($t1 | $a1);
         srl $a1, $t0, 2     |  $a1 = ($t0 >> 2);      // shift in 0's
         bclr $a0, $a0, 1    |  $a0 = $a0 & ~(1 << 1); // clear bit 1
         sb $t0, 0($a0)      |  Mem[$a0] = $t0;
         sb $a1, 1($a0)      |  Mem[$a0 + 1] = $a1;
         bset $t1, $t1, 10   |  $t1 = $t1 | (1 << 10); // set bit 10
         btst $t1, $t1, 10   |  $t1 = ($t1 & (1 << 10)) == 0 ? 1 : 0;
         slt $v2, $v0, $a1   |  $v2 = $v0 < $a1 ? 1 : 0;   // signed operands
         sltu $v3, $v0, $a1  |  $v3 = $v0 < $a1 ? 1 : 0;   // unsigned operands