Team ???:
From Ece
Project Proposal
- Team Name and Members:
Name: Team Chargers
Team Leader: Pavan Kumar Palacharla (pp302@msstate.edu)
Team Member: Ananth Ramchandran (ar564@msstate.edu)
- Design Overview:
Our basic aim is to design the 16 bit pipelined RISC processor which is capable of executing 15 and more instructions. In our initial proposal, we plan to declare the 15 instructions we are using. Clocking Methodology is Falling edge triggered. Numbers of registers in the register file are 8 as the fields rs, rt and rd are of size 3 bits each.
2.1 Instruction Formats
R-Format:
Opcode |
rs |
rt |
rd |
Function |
4 Bits 3 Bits 3 Bits 3 Bits 3 Bits
I-Format:
Opcode |
rs |
rt |
Immediate |
4 Bits 3 Bits 3 Bits 6 Bits
J-Format:
Opcode |
Address |
4 Bits 12 Bits
2.2 Instructions:
Name |
Mnemonic |
Operation |
Opcode |
Function |
Format |
Addition |
Add |
add $s1,$s2,$s3 |
0000 |
000 |
R |
Subtraction |
Sub |
sub $s1,$s2,$s3 |
0001 |
001 |
R |
Addition Immediate |
Addi |
addi $s1,$s2,30 |
0010 |
xxx |
I |
Load word |
lw |
lw $s1,4($s2) |
0011 |
Xxx |
I |
Store word |
Sw |
sw $s1,4($s2) |
0100 |
xxx |
I |
And |
and |
and $s1,$s2,$s3 |
0101 |
010 |
R |
Or |
Or |
or $s1,$s2,$s3 |
0110 |
011 |
R |
Nor |
Nor |
nor $s1,$s2,$s3 |
0111 |
100 |
R |
Xor |
xor |
xor $s1,$s2,$s3 |
1000 |
101 |
R |
Shift Left |
Sll |
sll $s1,$s2,4 |
1001 |
xxx |
I |
Shift Right |
Srl |
srl $s1,$s2,4 |
1010 |
xxx |
I |
Branch on Less Than Or Equal To |
Ble |
ble$s1,$s2,10 |
1011 |
xxx |
I |
Branch On Not Equal |
Bne |
bne $s1,$s2,10 |
1100 |
xxx |
I |
Set On Less |
Slt |
slt $s1,$s2,$s3 |
1101 |
110 |
R |
Jump |
J |
j 10 |
1110 |
Xxx |
J |
2.3 Register Table:
Registers |
Register Number |
$a0 |
000 |
$a1 |
001 |
$t0 |
010 |
$t1 |
011 |
$v0 |
100 |
$v1 |
101 |
$v3 |
110 |
$v4 |
111 |
Pseudo code:
while ($a1 > 0) do {
$a1 = $a1 –1;
$t0 = Mem[$a0];
if ($t0 > 0100hex) then {
$v0 = $v0 ÷ 8;
$v1 = $v1 | $v0; //or
Mem[$a0] = FF00hex;
}
else {
$v2 = $v2 × 4;
$v3 = $v3 ⊕ $v2; //xor
Mem[$a0] = 00FFhex;
}
$a0 = $a0 + 2;
}
return;
Assembly and machine code:
Assembly |
Machine code |
START: sub $t1,$t1,$t1 |
0001011011011000 : 16D8 |
addi $t1, $t1,1 |
0010110110000001 : 2D81 |
slt $t0, $a1,$0 |
1010010001000000 : A440 |
bne $t0,$t1,label |
1100010011Address[label] |
RETURN |
|
label: Addi $a1,$a1,-1 |
0010001001111111 : 227F |
lw $t0,0[$a0] |
0011000010000000 : 3080 |
Sll $t1, $t1,8 |
1001011011001000 : 96C8 |
Ble $t0,$t1,Else |
1011010011Address[Else] |
Srl $v0,$v0,3 |
1010100100000011 : A903 |
Or $v1,$v1,$v0 |
0110101101100000 : 6B60 |
Sub $t1,$t1,$t1 |
0001011011011001 : 16D9 |
Sub $t0,$t0,$t0 |
0001010010010001 : 1491 |
Addi $t0, $t0,1 |
0010010010000001 : 2481 |
Sll $t0,$t0,8 |
1001010010001000 : 9488 |
Sub $t1,$t1,$t0 |
0001011011010001 : 16D1 |
Sw $t1,0[$a0] |
0100000011000000 : 40C0 |
Else: Sll $v2,$v2,2 |
1001110110000010 : 9D02 |
Xor $v3,$v3,$v2 |
1000111111110101 : 8FF5 |
Sll $t1,$t1,8 |
1001011011001000 : 96C4 |
Addi $t1,$t1,-1 |
0010011011111111 : 26FF |
Sw $t0, 0[a0] |
0100000010000000 : 4080 |
Addi $a0,$a0,2 |
0010000000000010 : 2002 |
Jump START |
1110Address[START] |
Tasks and Schedule:
Name |
Task |
1st week |
2nd week |
3rd week |
4th week |
5th week |
Pavan |
Instruction set design, data path design, coding Web updateReport |
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|
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Ananth |
Instruction set design, hazard detection unit design, forwarding unit design, coding Web updateReport |
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------- ------- |
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Planned Meetings:
We plan to meet on Mondays and Thursdays
Mon-6:30pm to8:00 pm November 2, 9, 16
Thu-6:30pm to8:00 pm October 29, 5, 12, 19
