Team 1337:
From Ece
Contents |
Team 1337
- Team member: Jonathan Chapman
- Team member: Austin Lee
- Team member: Josh Richardson
Design Overview
We are building a 16-bit processor. This means the instruction memory, data memory, and registers will all be 16-bits. Due to the fact that we are using 3-bits for rs, rt, and rd we can have no more than 8 registers. Of these eight registers, we will reserve one for the zero register. Our clocking methodology will be a rising-edge triggered methodology except on write-back which will be falling-edge triggered. Team 1337's language of choice for this project is Verilog.
Instruction format
Example:
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R-Format: |
Opcode |
Rs |
rt |
rd |
Func |
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4 bits |
3 bits |
3 bits |
3 bits |
3 bits |
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Opcode |
Rs |
rt |
immediate |
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I–Format: |
4 bits |
3 bits |
3 bits |
6 bits |
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J- Format: |
Opcode |
address |
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4 bits |
12 bits |
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Instructions
Example:
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Name |
Mnemonic |
Operation |
Opcode |
Funct |
Format |
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No Operation |
nop |
No Operation |
0000 |
X |
J |
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Add |
add |
add $s1, $s2, $s3; $s1 = $s2 + $s3 |
0001 |
000 |
R |
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Add Immediate |
addi |
addi $s1, $s2 immediate; $s1 = $s2 + immediate |
0010 |
X |
I |
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And |
and |
and $s1, $s2, $s3; $s1 = $s2 & $s3 |
0001 |
001 |
R |
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Branch Equal |
beq |
beq $s1, $s2, addy ; if ($s1 == $s2) PC=PC+2+( addy *2); |
0100 |
X |
I |
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Branch Not Equal |
bne |
bne $s1, $s2, addy ; if ($s1 != $s2) PC=PC+2+( addy *2) |
0101 |
X |
I |
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Branch Not Zero |
bnz |
bnz $s1 addy ; if ($s1 != 0) PC=PC+2+( addy *2)
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0110 |
X |
I
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Branch Zero |
bz |
bz $s1 addy ; if ($s1 == 0) PC=PC+2+( addy *2)
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0111 |
X |
I |
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Jump |
jump |
jump address; PC = address
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1000 |
X |
J |
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Load Word |
lw |
lw $s1, num($s2); $s1 = mem [$s2+num] |
0011 |
X |
I |
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Or |
or |
or $s1, $s2, $s3; $s1 = $s2 | $s3 |
0001 |
010 |
R |
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Or Immediate |
ori |
ori $s1, $s2, immediate; $s1 = $s2 | immediate |
1001 |
X |
I |
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Set Equal |
seq |
seq $s1, $s2, $s3; if($s2 == $s3) $s1 = 1; else $s1 = 0;
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0010 |
011 |
R |
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Set Less Than immediate |
slti |
slti $s1, $s2, number; if($s2 < number) $s1 = 1; else $s1 = 0;
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1101 |
X |
I |
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Set Less Than or Equal To |
sle |
sle $s1, $s2, $s3; if($s2 <= $s3) $s1 = 1; else $s1 = 0;
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0010 |
101 |
R |
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Shift Left Immediate |
sll |
sll $s1, $s2, immediate; $s1 = $s2 << immediate |
1010 |
X |
I |
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Shift Right Immediate |
srl |
srl $s1, $s2, immediate; $s1 = $s2 >> immediate |
1011 |
X |
I |
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Store Word |
sw |
sw $s1, num($s2); mem [$s1+num] = $s2 |
1100 |
X |
I |
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Subtract |
sub |
sub $s1, $s2, $s3; $s1 = $s2 xor $s3
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0001 |
110 |
R |
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Xor |
xor |
xor $s1, $s2, $s3; $s1 = $s2 ^ $s3
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0001 |
111 |
R |
Pseudocode for the test program
$zero=0000hex; // Reg 0
$v0 = 0040hex; // Reg 1
$v1 = 1010hex; // Reg 2
$v2 = 000Fhex; // Reg 3
$v3 = 00F0hex; // Reg 4
$t0 = 0000hex; // Reg 5
$a0 = 0010hex; // Reg 6
$a1 = 0005hex; // Reg 7
while ($a1 > 0) do {
$a1 = $a1 –1;
$t0 = Mem [ $a0];
if ($t0 > 0100hex) then {
$v0 = $v0 ÷ 8;
$v1 = $v1 | $v0; //or
Mem [ $a0] = FF00hex;
}
else {
$v2 = $v2 • 4;
$v3 = $v3 • $v2; // xor
Mem [ $a0] = 00FFhex;
}
$a0 = $a0 + 2;
}
return;
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WhileLoop : |
//branch back up to here for while loop |
2 |
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slti |
$t0, $a1, 1 |
4 |
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bne |
$t0, $zero, end |
6 |
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addi |
$a1, $a1, -1 |
8 |
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lw |
$t0, 0($a0) |
10 |
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if |
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12 |
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slti |
$t0, $t0, 0x4 |
14 |
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bne |
$t0, $zero, else |
16 |
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srl |
$v0, $v0, 3 |
18 |
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or |
$v1, $v1, $v0 |
20 |
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addi |
$t0, $zero, 63 |
22 |
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sll |
$t0, $t0, 6 |
24 |
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addi |
$t0, $t0, 48 |
26 |
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sll |
$t0, $t0, 4 |
28 |
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sw |
$t0, 0($a0) |
30 |
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j |
endofelse |
32 |
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else |
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34 |
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sll |
$v2, $v2, 2 |
36 |
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xor |
$v3, $v3, $v2 |
38 |
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addi |
$t0, $zero, 63 |
40 |
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sll |
$t0, $t0, 6 |
42 |
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addi |
$t0, $t0, 48 |
44 |
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srl |
$t0, $t0, 4 |
46 |
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sw |
$t0, 0($a0) |
48 |
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endofelse |
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50 |
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addi |
$a0, $a0, 2 |
52 |
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j |
While Loop |
54 |
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end |
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56 |
Assembly Language
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Assembly Language |
Machine Code |
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slti $t0, $a1, 1 |
1101 101 111 000001 |
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bne $t0, $zero, end |
0101 000 000 011000 |
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addi $a1, $a1, -1 |
0010 111 111111111 |
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lw $t0, X($a0) |
0011 101 000010000 |
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slti $t0, $t0, 0x4 |
1101 101 101 000010 |
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bne $t0, $zero, else |
0101 101 000 001000 |
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srl $v0, $v0, 3 |
1011 001 001 000011 |
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or $v1, $v1, $v0 |
0001 010 001 010 010 |
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addi $t0, $zero, 63 |
0010 101 000 111111 |
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sll $t0, $t0, 6 |
1010 101 101 000110 |
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addi $t0, $t0, 48 |
0010 101 101 110000 |
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sll $t0, $t0, 4 |
1010 101 101 000100 |
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sw $t0, X($a0) |
1100 101 000010000 |
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j endofelse |
1000 000000110010 |
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sll $v2, $v2, 2 |
1010 011 011 000010 |
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xor $v3, $v3, $v2 |
0001 100 011 100 111 |
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addi $t0, $zero, 63 |
0010 101 000 111111 |
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srl $t0, $t0, 4 |
1011 101 101 000100 |
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addi $t0, $t0, 48 |
0010 101 101 110000 |
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sll $t0, $t0, 4 |
1010 101 101 000100 |
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sw $t0, X($a0)
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1100 101 000010000 |
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addi $a0, $a0, 2
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0010 110 110 000010 |
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j While Loop
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1000 000000000010 |
Tasks and Schedule
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Name |
Tasks |
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Jonathan Chapman |
Control Unit |
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Austin Lee |
Datapath |
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Josh Richardson |
Web Design |
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All |
Instruction Report Coding |
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Planned Meetings
The design team will meet every Tuesday at 5:15 p.m. until the project is completed.
November 2, 2010 Met from 1715 - 2030. All members were present.
November 9, 2010 Met from 1715 - 1930. All members were present.
November 16, 2010 Met from 17:15 - 2000. All members were present.
November 23, 2010 Met from 17:15 - 2400. All members were present.
November 24, 2010 Met from 08:15 - 13:30. All members were present.
November 29, 2010 Met from 09:00 - 01:00 on 30 November. All members were present until 17:00. Austin and Josh remained until 01:00 on 30 November.
