Team A++:
From Ece
Contents |
Team Name and Members
Team name: A++
Team leader: Kevin Anderson
Team member: Aaron Boudreaux
Team member: Patrick Hernandez
Design Overview
Every operation will be performed on the rise of the clock, except the reading of the registers will be done on the falling of the clock. Since our rs, rt, and rd fields will be 3 bits we will have the ability to access 8 registers. The 0 register will be hard coded to the value 0 to be used for comparisons and branching. This implementation is a 16-bit architecture so our instruction memory and data memory will be limited to 2^16 instructions. We will be completing this implementation using Java.
Instruction Format
R-Format
| OpCode | Rs | Rt | Rd | Func |
| 4 bits | 3 bits | 3 bits | 3 bits | 3 bits |
I-Format
| OpCode | Rs | Rt | Immediate |
| 4 bits | 3 bits | 3 bits | 6 bits |
J-Format
| OpCode | Offset |
| 4 bits | 12 bits |
Instructions
| Name | Mnemonic | Operation | Opcode | Func | Format |
| no operation | nop | nothing | 1111 | XXX | X |
| add | add | add $s1, $s2, $s3; $s1= $s2 + $s3 |
0000 | 000 | R |
| add immediate | addi | addi $s1, $s2, 100 $s1 = $s2 + 100 |
0001 | XXX | I |
| subtract | sub | sub $s1, $s2, $s3 $s1 = $s2 - $s3 |
0000 | 001 | R |
| and | and | and $s1, $s2, $s3 $s1 = $s2 & $s3 |
0000 | 010 | R |
| and immediate | andi | andi $s1, $s2, 100 $s1 = $s2 & 100 |
0010 | XXX | I |
| or | or | or $s1, $s2, $s3 $s1 = $s2 | $s3 |
0000 | 011 | R |
| or immediate | ori | ori $s1, $s2, 100 $s1 = $s2 | 100 |
0011 | XXX | I |
| exclusive or | xor | xor $s1, $s2, $s3 $s1 = $s2 ^ $s3 |
0000 | 100 | R |
| exclusive or immediate | xori | xori $s1, $s2, 100 $s1 = $s2 | 100 |
0100 | XXX | I |
| not or | nor | nor $s1, $s2, $s3 $s1 = !($s2 | $s3) |
0000 | 101 | R |
| not or immediate | nori | nor $s1, $s2, 100 $s1 = !($s2 | 100) |
0101 | XXX | I |
| set less than immediate | slti | slti $s1, $s2, 100 if ($s2 < 100) $1 = 1 else $1 = 0 |
0110 | XXX | I |
| load word | lw | lw $1, offset($2) | 0111 | XXX | I |
| store word | sw | sw $1, offset($2) | 1000 | XXX | I |
| branch on equal | beq | beq $1, $2, 100 if ($1 == $2) PC = PC + 4 + 100 |
1001 | XXX | I |
| jump | j | j 100 PC = 100 |
1010 | XXX | J |
| branch on not equal | bne | bne $1, $2, 100 if ($1 != $2) PC = PC + 4 + 100 |
1011 | XXX | I |
| set less than | slt | slt $1, $2, $3 if ($2 < $3) $1 = 1 else $1 = 0 |
0000 | 110 | R |
Assembly language and machine code for the test program (Pseudocode)
s1 = s2 + s3;
s1 = s2 + 1;
s1 = s2 - s3;
s1 = s2 & s3;
s1 = s2 & 1;
s1 = s2 | s3;
s1 = s2 | 1;
s1 = s2 ^ s3;
s1 = s2 ^ 1;
s1 = !(s2 | s3);
s1 = !(s2 | 1);
if (s1 < 1)
{
s1 = s2 + s3;
}
else
{
s1 = s2 - s3;
}
s1 = s2;
s2 = s1;
LABEL:
if (s1 == s2)
{
s1 = s2 + 1;
goto LABEL;
}
if (s1 != s2)
{
s1 = s2 + 1;
}
if (s1 < s2)
{
s1 = s2 + s3;
}
| Assembly Language | Machine Code |
| add $s1, $s2, $s3 | 04C8: 0000 010 011 001 000 |
| addi $s1, $s2, 1 | 1441: 0001 010 001 000 001 |
| sub $s1, $s2, $s3 | 04C9: 0000 010 011 001 001 |
| and $s1, $s2, $s3 | 04CA: 0000 010 011 001 010 |
| andi $s1, $s2, 1 | 2441: 0010 010 001 000 001 |
| or $s1, $s2, $s3 | 04CB: 0000 010 011 001 011 |
| ori $s1, $s2, 1 | 3441: 0011 010 001 000 001 |
| xor $s1, $s2, $s3 | 04CC: 0000 010 011 001 100 |
| xori $s1, $s2, 1 | 4441: 0100 010 001 000 001 |
| nor $s1, $s2, $s3 | 04CD: 0000 010 011 001 101 |
| nori $s1, $s2, 1 | 5441: 0101 010 001 000 001 |
| slti $s4, $s1, 1 | 6301: 0110 001 100 000 001 |
| beq $s1, $zero, 4 | 9044: 1001 000 001 000 100 |
| add $s1, $s2, $s3 | 04C8: 0000 010 011 001 000 |
| sub $s1, $s2, $s3 | 04C9: 0000 010 011 001 001 |
| lw $s1, 0($s2) | 7440: 0111 010 001 000 000 |
| sw $s1, 0($s2) | 8440: 1000 010 001 000 000 |
| bne $s1, $s2, 8 | B448: 1011 010 001 001 000 |
| addi $s1, $s2, 1 | 1441: 0001 010 001 000 001 |
| jump LABEL | A048: 1010 000 001 001 000 |
| slt $s4, $s1, $s2 | 02A6: 0000 001 010 100 110 |
| beq $s4, $zero, 4 | 9104: 1001 000 100 000 100 |
| add $s1, $s2, $s3 | 04C8: 0000 010 011 001 000 |
| nop | FFFF: 1111 111 111 111 111 |
Tasks and Schedule
| Name | Task | Week 1 | Week 2 | Week 3 | Week 4 | Week5 |
| Aaron Boudreaux | IF, ID, EXE Testing |
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| Kevin Anderson | Data Hazard, Forwarding Unit Testing |
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| Patrick Hernandez | MEM, WB, Control Testing |
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Group Meetings
The design team will meet on the following dates to discuss the project progress and assigned tasks:
October 26th, 5 pm - 7:30 pm, All members present
November 3rd, 5 pm - 7:30 pm, All members present
November 9th, 5 pm - 6:15 pm, All members present
November 22nd, 5 pm - 7 pm, All members present
November 23rd, 4 pm - 11 pm, All members present
Final presentation meeting: November 30th, 5 pm - 5:30 pm
Datapath
Classes
IfIdBuffer
- variables:
- 16 character string instructionWord
- boolean writeEnabled
- 16 character string pCounter
- functions:
- 16 character string getInstructionWord()
- void setInstructionWord(string pInstructionWord)
setInstructionWord checks writeEnabled is true before setting - void setWriteEnabled(boolean writeEnabled)
IdExBuffer
- variables:
- 16 character string pCounter
- 1 character string RegDest
- 3 character string AluOp
- 1 character string AluSrc
- 1 character string Branch
- 1 character string MemRead
- 1 character string MemWr
- 1 character string RegWr
- 1 character string MemToReg
- 3 character string Rs
- 3 character string Rt
- 3 character string Rd
- 16 character string Immediate
- 16 character string read1
- 16 character string read2
- functions:
- getters/setters for all variables
ExMemBuffer
- variables:
- 16 character string pCounter
- 1 character string Branch
- 1 character string MemRead
- 1 character string MemWr
- 1 character string RegWr
- 1 character string MemToReg
- 16 character string AluOut
- 16 character string read2
- 3 character string regWrAddr
- 1 character string aluZero
- functions:
- getters/setters for all variables
MemWbBuffer
- variables:
- 1 character string RegWr
- 1 character string MemToReg
- 16 character string AluOut
- 16 character string memOut
- 3 character string regWrAddr
- functions:
- getters/setters for all variables
InstructionMemory
- variables:
- vector<16 character string> memory
- functions:
- character string getMemory(string address)
- void insertMemory(string instruction)
Registers
- variables:
- 16 character string[8] memory
- functions:
- void write(3 character string address, 16 character string data)
- 16 character string[2] read(3 character string address,3 character string address)
DataMemory
- variables:
- vector<16 character string> memory
- functions:
- 16 character string read(16 character string address)
- void write(16 character string address, 16 character string data);
In addition to these classes there will be a function for each stage in the pipeline that will access these classes for their needed information.
TODO
Debugging/Testing
Completed
Forwarding Unit function
Hazard Detection Unit function
IF function
ID function
EX function
MEM function
WB function
IfIdBuffer class
IdExBuffer class
ExMemBuffer class
MemWbBuffer class
InstructionMemory class
Registers class
DataMemory class
