Team Alpha:
From Ece
Team Alpha
- Team Leader: Russ Ward
- Team Member: Richard Teeple
- Team Member: Zack Krampf
Design Overview
The design of this 16-bit processor is based highly on the MIPS processor with many notable changes. We have chosen to use 16 registers, which requires the use of 4 bit addressing for each register. To allow for the best use of each instruction, we are using 5 different formats. The greater number of formats allows for the best use of the 16-bit codes. The formats are detailed below.
This processor is rising edge triggered and allows the use 19 different instructions. <p>
Instruction Format
| R-Format: | op | rs | rt | rd | |
| 4 bits | 4 bits | 4 bits | 4 bits | ||
| RF-Format: | op | rs | rt | funct | |
| 4 bits | 4 bits | 4 bits | 4 bits | ||
| J-Format: | op | address | |||
| 4 bits | 12 bits | ||||
| I-Format: | op | r | immediate | ||
| 4 bits | 4 bits | 8 bits | |||
| LI-Format: | op | r | immediate | ||
| 4 bits | 4 bits | 8 bits | |||
- Note that the difference between the R and RF format is that the RF Format extends the opcode by utilizing a function code. The output of RF and I formats commands is written to the accumulation register. Like the RF format, the I format either reads data from or writes data to the accumulation register based on the opcode called. The difference between the LI and I formats, is that the LI format is used for loading data into the registered specified and not the accumulation register.
Instructions
The following instructions are included in the processor:
| Name | Mnem | Operation | Opcode | Func | Format | |
| NOP | nop | nop | No Operation | 0000 | xxxx | - |
| Add | add | add $s1, $s2 | acc = $s1 + $s2 | 0001 | 0000 | RF |
| Subtract | sub | sub $s1, $s2 | acc = $s1 - $s2 | 0001 | 0001 | RF |
| Or | or | or $s1, $s2 | acc = $s1 | $s2 | 0001 | 0010 | RF |
| XOR | xor | xor $s1, $s2 | acc = $s1 (+) $s2 | 0001 | 0011 | RF |
| Move | move | move $s1, $s2 | $s1 = $s2 | 0001 | 0100 | RF |
| Shift Left Logical | sll | sll $s0, NUM | $s0 << NUM | 0010 | xxxx | I |
| Shift Right Logical | srl | srl $s0, NUM | $s0 << NUM | 0011 | xxxx | I |
| Load Word | lw | lw $s0, $s1, $s2 | $s0 = $s1[$s2+2] | 0100 | xxxx | R |
| Store Word | sw | sw $s0, $s1, $s2 | $s0[$s1+2] = $s2 | 0101 | xxxx | R |
| Add Immediate | addi | addi $s0, NUM | acc = $s0 + NUM | 0110 | xxxx | I |
| Or Immediate | ori | ori $s0, NUM | acc = $s0 | NUM | 1100 | xxxx | I |
| Set Less Than Immediate | slti | slti $s0, NUM | if ($s0 < NUM) acc = 1 if ($s0 >= NUM) acc = 0 | 1101 | xxxx | I |
| Set Greater Than Immediate | sgti | sgti $s0, NUM | if ($s0 > NUM) acc = 1 if ($s0 <= NUM) acc = 0 | 0111 | xxxx | I |
| Branch Equal | beq | beq $s0, NUM | if ($s0 == acc) PC = PC + 2 + NUM | 1000 | xxxx | I |
| Load Lower Immediate | lli | lli $s0, NUM | $s0[7:0] = NUM | 1001 | xxxx | LI |
| Load Upper Immediate | lui | lui $s0, NUM | $s0[15:8] = NUM | 1010 | xxxx | LI |
| Jump | j | j ADDR | goto ADDR | 1011 | xxxx | J |
| Branch Greater Than | bgt | bgt $s0, NUM | if ($s0 > acc) PC = PC + 2 + NUM | 1110 | xxxx | I |
Assembly language and machine code for the test program
| Line | Assembly Language | Machine Code |
| 0 0000 0001 | lui $v0, 00 | A100: 1010 0001 0000 0000 |
| 0 0000 0010 | lli $v0, 40 | 9140: 1001 0001 0100 0000 |
| 0 0000 0011 | lui $v1, 10 | A210: 1010 0010 0001 0000 |
| 0 0000 0100 | lli $v1, 10 | 9210: 1001 0010 0001 0000 |
| 0 0000 0101 | lui $v2, 00 | A300: 1010 0011 0000 0000 |
| 0 0000 0110 | lli $v2, 0F | 930F: 1001 0011 0000 1111 |
| 0 0000 0111 | lui $v3, 00 | A400: 1010 0100 0000 0000 |
| 0 0000 1000 | lli $v3, F0 | 94F0: 1001 0100 1111 0000 |
| 0 0000 1001 | lui $t0, 00 | A500: 1010 0101 0000 0000 |
| 0 0000 1010 | lli $t0, 00 | 9500: 1001 0101 0000 0000 |
| 0 0000 1011 | lui $a0, 00 | A600: 1010 0110 0000 0000 |
| 0 0000 1100 | lli $a0, 10 | 9610: 1001 0110 0001 0000 |
| 0 0000 1101 | lui $a1, 00 | A700: 1010 0111 0000 0000 |
| 0 0000 1110 | lli $a1, 05 | 9705: 1001 0111 0000 0101 |
| WHILE | sgti $a1, 0 | 7700: 0111 0111 0000 0000 |
| 0 0001 0000 | beq $zero, ENDWHILE | 802B: 1000 0000 0010 1011 |
| 0 0001 0001 | addi $a1, -1 | 6781: 0110 0111 1000 0001 |
| 0 0001 0010 | move $a1, $acc | 17F4: 0001 0111 1111 0100 |
| 0 0001 0011 | move $acc, $zero | 1F04: 0001 1111 0000 0100 |
| 0 0001 0100 | lw $t0, $a0 | 4560: 0100 0101 0110 0000 |
| 0 0001 0101 | lui $s0, 01 | A801:1010 1000 0000 0001 |
| 0 0001 0110 | lli $s0, 00 | 9800: 1001 1000 0000 0000 |
| 0 0001 0111 | addi $s0, 0 | 6800: 0110 1000 0000 0000 |
| 0 0001 1000 | bgt $t0, IF | E521: 1110 0101 0010 0001 |
| ELSE | sll $v2, 2 | 2302: 0010 0011 0000 0010 |
| 0 0001 1010 | xor $v3, $v2 | 1433: 0001 0100 0011 0011 |
| 0 0001 1011 | move $v3, $acc | 14F4: 0001 0100 1111 0100 |
| 0 0001 1100 | lui $s1, 00 | A900: 1010 1001 0000 0000 |
| 0 0001 1101 | lli $s1, FF | 99FF: 1001 1001 1111 1111 |
| 0 0001 1110 | move $acc, $zero | 1F04: 0001 1111 0000 0100 |
| 0 0001 1111 | sw $s1, $a0 | 5690: 0101 0110 1001 0000 |
| 0 0010 0000 | j ENDIF | B028: 1011 0000 0010 1000 |
| IF | srl $v0, 3 | 3103: 0011 0001 0000 0011 |
| 0 0010 0010 | or $v1, $v0 | 1212: 0001 0010 0001 0010 |
| 0 0010 0011 | move $v1, $acc | 12F4: 0001 0010 1111 0100 |
| 0 0010 0100 | lui $s1, FF | A9FF: 1010 1001 1111 1111 |
| 0 0010 0101 | lli $s1, 00 | 9900: 1001 1001 0000 0000 |
| 0 0010 0110 | move $acc, $zero | 1F04: 0001 1111 0000 0100 |
| 0 0010 0111 | sw $s1, $a0 | 5690: 0101 0110 1001 0000 |
| ENDIF | addi $a0, 2 | 6602: 0110 0110 0000 0010 |
| 0 0010 1001 | move $a0, $acc | 16F2: 0001 0110 1111 0010 |
| 0 0010 1010 | j WHILE | B00F: 1011 0000 0000 1111 |
| ENDWHILE |
Tasks and Schedule
| Name | Tasks | Schedule | ||||
| 1st Week | 2nd Week | 3rd Week | 4th Week | 5th Week | ||
| Russ Ward | Proposal | |||||
| Instructions | ||||||
| Datapath | ||||||
| Control Unit | ||||||
| Coding | ||||||
| Web Design | ||||||
| Richard Teeple | Proposal | |||||
| Instructions | ||||||
| Datapath | ||||||
| Control Unit | ||||||
| Coding | ||||||
| Report | ||||||
| Zack Krampf | Proposal | |||||
| Instructions | ||||||
| Datapath | ||||||
| Control Unit | ||||||
| Coding | ||||||
| Report | ||||||
Planned Meetings
| Planned Meetings: | |
| Sunday, October 25th 19:30 – 22:30 | Met. Worked on proposal. |
| Monday, October 26th 20:00 – 22:15 | Met. Worked on proposal. |
| Thursday, October 29th 20:00 – 22:00 | Canceled due to conflicts. Worked individually. |
| Sunday, November 1st 20:00 - 21:30 | Canceled due to conflicts. Worked individually. |
| Thursday, November 5th 17:00 - 18:30 | Met. Worked on datapath and control unit. |
| Sunday, November 8th 20:00 - 21:30 | Canceled due to test and homework. |
| Thursday, November 12th 17:00 - 18:30 | Met. Worked on program layout. |
| Sunday, November 15th 20:00 - 21:30 | |
| Thursday, November 19th 17:00 - 18:30 | |
| Sunday, November 22th 20:00 - 21:30 |
Team Meetings and Attendance
| Planned Meetings: | Russ Ward | Richard Teeple | Zack Krampf |
| Sunday, October 25th 19:30 – 22:30 | X | X | X |
| Monday, October 26th 20:00 – 22:15 | X | X | X |
| Thursday, November 5th 17:00 – 18:30 | X | X | X |
| Thursday, November 12th 18:00 – 20:00 | X | X | X |
| Sunday, November 15th 18:00 – 20:00 | X | X | |
| Tuesday, November 17th 17:00 – 19:00 | X | X | |
| Thursday, November 19th 17:00 – 19:30 | X | X | X |
| Sunday, November 22nd 18:00 – 18:45 | X | X |
Datapath and Control Diagram
Based on Figure 4.65 from the textbook.
Basic Program Layout and Results
We decided to create a "main" program that calls functions from other perl files to emulate the MIPS processor. We first started by making the "main" program read and interpret the input, given in binary and read from "input.txt". The following output is generated by the "main" program with the input given in "Assembly language and machine code for the test program" section above:
| 1 | 1010000100000000 | opcode: 1010 | Format: LI | lui $1 0 (0x0) |
| 2 | 1001000101000000 | opcode: 1001 | Format: LI | lli $1 64 (0x40) |
| 3 | 1010001000010000 | opcode: 1010 | Format: LI | lui $2 16 (0x10) |
| 4 | 1001001000010000 | opcode: 1001 | Format: LI | lli $2 16 (0x10) |
| 5 | 1010001100000000 | opcode: 1010 | Format: LI | lui $3 0 (0x0) |
| 6 | 1001001100001111 | opcode: 1001 | Format: LI | lli $3 15 (0xF) |
| 7 | 1010010000000000 | opcode: 1010 | Format: LI | lui $4 0 (0x0) |
| 8 | 1001010011110000 | opcode: 1001 | Format: LI | lli $4 240 (0xF0) |
| 9 | 1010010100000000 | opcode: 1010 | Format: LI | lui $5 0 (0x0) |
| 10 | 1001010100000000 | opcode: 1001 | Format: LI | lli $5 0 (0x0) |
| 11 | 1010011000000000 | opcode: 1010 | Format: LI | lui $6 0 (0x0) |
| 12 | 1001011000010000 | opcode: 1001 | Format: LI | lli $6 16 (0x10) |
| 13 | 1010011100000000 | opcode: 1010 | Format: LI | lui $7 0 (0x0) |
| 14 | 1001011100000101 | opcode: 1001 | Format: LI | lli $7 5 (0x5) |
| 15 | 0111011100000000 | opcode: 0111 | Format: I | sgti $7 0 (0x0) |
| 16 | 1000000000101011 | opcode: 1000 | Format: I | beq $0 43 (0x2B) |
| 17 | 0110011110000001 | opcode: 0110 | Format: I | addi $7 129 (0x81) |
| 18 | 0001011111110100 | opcode: 0001 | Format: RF | move $7 $15 |
| 19 | 0001111100000100 | opcode: 0001 | Format: RF | move $15 $0 |
| 20 | 0100010101100000 | opcode: 0100 | Format: R | lw $0 $5 $6 |
| 21 | 1010100000000001 | opcode: 1010 | Format: LI | lui $8 1 (0x1) |
| 22 | 1001100000000000 | opcode: 1001 | Format: LI | lli $8 0 (0x0) |
| 23 | 0110100000000000 | opcode: 0110 | Format: I | addi $8 0 (0x0) |
| 24 | 1110010100100001 | opcode: 1110 | Format: I | bgt $5 33 (0x21) |
| 25 | 0010001100000010 | opcode: 0010 | Format: I | sll $3 2 (0x2) |
| 26 | 0001010000110011 | opcode: 0001 | Format: RF | xor $4 $3 |
| 27 | 0001010011110100 | opcode: 0001 | Format: RF | move $4 $15 |
| 28 | 1010100100000000 | opcode: 1010 | Format: LI | lui $9 0 (0x0) |
| 29 | 1001100111111111 | opcode: 1001 | Format: LI | lli $9 255 (0xFF) |
| 30 | 0001111100000100 | opcode: 0001 | Format: RF | move $15 $0 |
| 31 | 0101011010010000 | opcode: 0101 | Format: R | sw $0 $6 $9 |
| 32 | 1011000000101000 | opcode: 1011 | Format: J | j 40 (0x28) |
| 33 | 0011000100000011 | opcode: 0011 | Format: I | srl $1 3 (0x3) |
| 34 | 0001001000010010 | opcode: 0001 | Format: RF | or $2 $1 |
| 35 | 0001001011110100 | opcode: 0001 | Format: RF | move $2 $15 |
| 36 | 1010100111111111 | opcode: 1010 | Format: LI | lui $9 255 (0xFF) |
| 37 | 1001100100000000 | opcode: 1001 | Format: LI | lli $9 0 (0x0) |
| 38 | 0001111100000100 | opcode: 0001 | Format: RF | move $15 $0 |
| 39 | 0101011010010000 | opcode: 0101 | Format: R | sw $0 $6 $9 |
| 40 | 0110011000000010 | opcode: 0110 | Format: I | addi $6 2 (0x2) |
| 41 | 0001011011110010 | opcode: 0001 | Format: RF | or $6 $15 |
| 42 | 1011000000001111 | opcode: 1011 | Format: J | j 15 (0xF) |
