Team Chargers:

From Ece

Team Name

TEAM CHARGERS

Team Members

Pavan Kumar Palacharla
Ananth Ramchandran

Design Overview

Our basic aim is to design the 16 bit pipelined RISC processor which is capable of executing 15 and more instructions. In our initial proposal, we plan to declare the 15 instructions we are using. Clocking Methodology is Falling edge triggered. Numbers of registers in the register file are 8 as the fields rs, rt and rd are of size 3 bits each. We are writing the code in C++.

Instruction Format

R Format Instructions

Opcode	Rs	Rt	Rd	Func
4 Bits	3 bits	3 bits	3 bits	3 bits

I Format Instructions

Opcode	Rs	Rt	Immediate
4 Bits	3 Bits	3 Bits	6 Bits

J Format Instructions

Opcode	Immediate8
4 Bits	12 Bits

Instructions

Name	Mnemonic	Operation	Opcode	Function	Format
Addition	Add	add $s1,$s2,$s3	0000	000	R
Subtraction	Sub	sub $s1,$s2,$s3	0001	001	R
Addition Immediate	Addi	addi $s1,$s2,30	0010	xxx	I
Load word	Lw	lw $s1,4($s2)	0011	xxx	I
Store word	Sw	sw $s1,4($s2)	0100	xxx	I
And	And	and $s1,$s2,$s3	0101	010	R
Or	Or	or $s1,$s2,$s3	0110	011	R
Nor	Nor	nor $s1,$s2,$s3	0111	100	R
Xor	Xor	xor $s1,$s2,$s3	1000	101	R
Shift Left Logical	Sll	sll $s1,$s2,4	1001	xxx	I
Shift Right Logical	Srl	srl $s1,$s2,4	1010	xxx	I
Branch on Less Than Or Equal To	Ble	ble$s1,$s2,10	1011	xxx	I
Branch On Not Equal	Bne	bne $s1,$s2,10	1100	xxx	I
Set On Less Than	Slt	slt $s1,$s2,$s3	1101	110	R
Jump	J	j 10	1110	xxx	J
Terminate	Terminate	Stops the Program	1111	xxx

Registers

Registers	Register Number
$a0	000
$a1	001
$t0	010
$t1	011
$v0	100
$v1	101
$v3	110
$v4	111

Assembly Language & Machine Code for the Test Program

Pseudo code:

while ($a1 > 0) do {
$a1 = $a1 –1;
$t0 = Mem[$a0];
if ($t0 > 0100hex) then {
$v0 = $v0 ÷ 8;
$v1 = $v1 | $v0; //or
Mem[$a0] = FF00hex;
}
else {
$v2 = $v2 × 4;
$v3 = $v3 ⊕ $v2; //xor
Mem[$a0] = 00FFhex;
}
$a0 = $a0 + 2;
}
return;

Assembly and machine code:

Address	Instruction	Machine Code
X0000	sub $t1,$t1,$t1	0001 011 011 011 001 : 16D9
X0001	slt $t0,$a1,$t1	1101 010 001 011 110 :D45E
X0002	addi $t1,$t1,1	0010 011 011 000 001 :26C1
X0003	bne $t0,$t1,-1	1100 011 010 000 001 :C681
X0004	Terminate	1111 000 000 000 000 :F000
X0005	addi $a1,$a1,-1	0010 001 001 111 111 :227F
X0006	lw $t0,o[$a0]	0011 010 000 000 000 :3400
X0007	sll $t1,$t1,8	1001 011 011 001 000 :96C8
X0008	ble $t0,$t1,8	1011 011 010 001 001:B688
X0009	srl $v0,$v0,3	1010 100 100 000 011 :A903
X000A	or $v1,$v1,$v0	0110 101 101 100 011:6B61
X000B	sub $t1,$t1,8	0001 011 011 001 000 :16C8
X000C	sub $t1,$t1,$t1	0001 011 011 011 001 :16D9
X000D	addi $t0,$t0,1	0010 010 010 000 001:2481
X000E	sll $t0,$t0,8	1001 010 010 001 000:9488
X000F	sub $t1,$t1,$t0	0001 011 011 010 001:16D1
X0010	sw $t1,0[$a0]	0100 011 000 000 000:4600
X0011	Jump 23	1110 000 000 010 111 :E017
X0012	Else:sll $v2,$v2,2	1001 110 110 000 010:9D82
X0013	xor $v3,$v3,$v2	1000 111 111 110 101:8FF5
X0014	sll $t1,$t1,8	1001 011 011 001 000:96C8
X0015	adi $t1,$t1,-1	0010 011 011 111 111:26FF
X0016	sw $t0,0[$a0]	0100 010 000 000 000:4400
X0017	addi $a0,$a0,2	0010 000 000 000 010 :2002
X0018	Jump 16	1110 000 000 000 000:E000

Tasks & Schedule

Name

Task

1st week

2nd week

3rd week

4th week

5th week

Pavan

Instruction set design, data path design, coding

     Web    update

Report

Yes

Ananth

Instruction set design, hazard detection unit design, forwarding unit

design, coding

     Web update

Report

Yes

Team Contributions

Name	Date	WorkDone	Time
Pavan	29th Oct	Project Proposal	1hrs
Ananth	2nd Nov	Data Path	1hrs
Pavan	5th Nov	Control Unit	1hrs
Pavan,Ananth	9th Nov	Writing of C++ code	4hrs
Ananth	12th Nov	PC,Register file,ALU module	2hrs
Ananth	16th Nov	Sign Extend module,branch adder	1hrs
Pavan	19th Nov	IF/ID, ID/EX pipeline registes,EX/MEM, MEM/WB pipeline registers	2hrs
Pavan,Ananth	21st Nov	Forwarding Unit,combining modules	3hrs
Pavan,Ananth	24th Nov	Correction of errors,Final report	3 hrs

Team Meetings

We have met on Mondays and Thursdays
Mon-6:30pm to8:30 pm November 2,5,9, 12, 16,19, 21,22, 24
Thu-6:30pm to8:30 p m October 29

Datapath

Deliverables

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