Team Dynamik:
From Ece
PROJECT PROPOSAL
1. Team Name and Members
Team Name: “Dyanmik”
Team Leader: Roberto Orellana
Team Member: Ranjit Amgai
2. Design Overview
2.1 Instruction set
Arithmetic: Add, Subtract, Add immediate
Data transfer: Load, store
Logical: And, or, xor, not, shift left logical, shift right logical
Conditional branch: branch on not equal, branch if equal, set if less than,
Unconditional branch: jump
No Operation: nop
2.2 Clocking methodology: Rising edge triggered
2.3 Implementation Method: C++
2.4 Registers file: 8 ×16-bit register file Numbered 0 to 7.
$v0 = 000
$v1 = 001
$v2 = 010
$v3 = 011
$a0 = 100
$a1 = 101
$t0 = 110
$t1 = 111
2.5 Pipelining: 5 Stage: IF->ID->EX -> MEM->WB
2.6. Instruction format
|
R-Format: |
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|
|
|
Opcode |
Rs |
rt |
rd |
Func |
|
4 bits |
3 bits |
3 bits |
3 bits |
3 bits |
|
I-Format |
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|
|
|
Opcode |
Rs |
rt |
Constant or address |
|
4 bits |
3 bits |
3 bits |
6 bits |
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J- Format: |
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|
Opcode |
Adress |
|
4 bits |
12 bits |
|
Name |
Mnemonic |
Operation |
Opcode |
Function |
Format |
|
add |
add |
add $s1, $s2, $s3; $s1= $s2 + $s3; |
000 |
001 |
R |
|
and |
and |
and $s1,$s2, $s3; $s1= $s2 & $s3 |
0000 |
0010 |
R |
|
Add immediate |
addi |
addi $s1, $s2, -20; $s1= $s2-20 |
0001 |
000 |
I |
|
Branch if equal |
beq |
beq $s1, $s2, label; if($s1==$s2) PC= PC+4+BranchAddr |
0010 |
000 |
I |
|
Branch on not equal |
bne |
bne $s1, $s2, label; if($s1 != $s2) PC= PC+4+BranchAddr |
0011 |
000 |
I |
|
Branch if less than |
blt |
blt $s1, $s2, label; if($s1 < $s2) PC= PC+4+BranchAddr |
0100 |
000 |
I |
|
Jump |
j |
j label; PC=JumpAddr |
0101 |
000 |
J |
|
Load word |
lw |
lw $s1, (offset)$s2; $s1= Mem[offset+$S2] |
0110 |
000 |
I |
|
No operation |
nop |
nop; PC=PC+4 |
0111 |
000 |
I |
|
Or |
or |
or $s1, $s2, $s3; $s1= $s2 || $s3 |
0000 |
011 |
R |
|
Not |
not |
not $s1, $s2; $s1= !$s2 |
0000 |
100 |
R |
|
set if less than |
slt |
slt $s1, $s2, $s3; $s1= ($s2 < $s3)?1:0 |
0000 |
101 |
R |
|
Shift left logical |
sll |
sll $s1, $s2, ShAmt; $s1= $s2 << ShAmt |
1000 |
000 |
I |
|
Shift right logical |
srl |
srl $s1, $s2, ShAmt; $s1= $s2 >> ShAmt |
1001 |
000 |
I |
|
Store word |
sw |
sw $s1, (offset)$s2; Mem[$s2+offset]= $s1 |
1010 |
000 |
I |
|
Subtract |
sub |
sub $s1, $s2, $s3; $s1= $s2- $s3; |
0000 |
110 |
R |
|
XOR |
xor |
xor $s1, $s2, $s3; $s1= $s2 ^ $s3 |
0000 |
111 |
R |
2.7. Assembly language and machine code for the test program
//initial values
|
Instruction |
Machine Code |
|
addi $v0, $v0, 0x020 addi $v0, $v0, 0x020 //set v0 addi $v1, $v1, 1 sll $v1, $v1, 12 addi $v1, $v1, 16 addi $v2, $v2, 0xF // set v2 addi $v3, $v3, 1 sll $v3, $v3, 8 addi $v3, $v3, -16 addi $t0, $t0, 0 addi $a0, $a0, 0x10 addi $a1, $a1, 5 //end initial values Start: sub $t1, $t1, $t1 //set $t1 to zero blt $a1, $t1, down //mnemonic if($a1< $t1) jump to down addi $a1, $a1, -1 //$a1= $a1 – 1; lw $t0, 0($a0)
addi $t1, $t1, 1 //$t1=1 sll $t1, $t1, 8 //$t1=256 ->0x100
blt $t0, $t1, else //if($t0 < $t1) jump to else srl $v0, $v0, 3 //$v0=$v0 /8 or $v1, $v1, $v0 //$v1= $v1 | $v0
sub $t1, $t1, $t1 //set t1 to 0 addi $t1, $t1,1 //$t1=1 sll $t1, $t1, 8 //$t1= 256 addi $t1, $t1, -1 //$t1=255 sll $t1, $t1, 8 //$t1=255*256 -> 0xFF00 sw $t1, 0($a0) j down else: sll $v2, $v2,2 //$v2= $v2*4 xor $v3, $v3, $v2
sub $t1, $t1, $t1 //$t1=0 addi $t1, $t1, 1 //$t1=1 sll $t1, $t1, 8 //$t1= 256 addi $t1, $t1, -1 //$t1=255 -> 0x00FF sw $t1, 0($a0) down: addi $a0, $a0, 2 //$a0= $a0+2 J Start
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0x1020 0x1020 0x1241 0x824C 0x1250 0x148F 0x16C1 0x86C8 0x16F0 0x1D80 0x1910 0x1B45
0x0FFE
0x193F 0x6980
0x1FC1 0x8FC8
0x9003 0x004B
0x0FFE 0x1FC1 0x8FC8 0x1FFF 0x8FC8 0xA9C0
0x8482 0x069F
0x0FFE 0x1FC1 0x8FC8 0x1FFF 0xA9C0
0x1902 |
3. Task and Scheduling
Ranjit Amgai:
<img width=794 height=161 src="ControlUnitv2-1_files/image001.gif">
Roberto Orellana:
<img width=712 height=161 src="ControlUnitv2-1_files/image002.gif">
4. Planned Meetings
The team will meet on the following schedule
Friday Oct 30 2.00 pm to 5.30 pm
Saturday Oct31 2.00 pm to 5.30 pm
Friday Nov 6 2.00 pm to 5.30 pm
Saturday Nov 7 2.00 pm to 5.30 pm
Friday Nov 13 2.00 pm to 5.30 pm
Saturday Nov 14 2.00 pm to 5.30 pm
Friday Nov 20 2.00 pm to 5.30 pm
Saturday Nov 21 2.00 pm to 5.30 pm
Friday Nov 27 2.00 pm to 5.30 pm
Saturday Nov 28 2.00 pm to 5.30 pm
Note: Team members may meet more number of times if required.
5. Team Name
“DYNAMIK”
|
Opcode |
Reg- Dst |
ALU- Src |
Mem toReg |
Reg_ Wrt |
Mem_ Read |
MemWrt |
Branch |
Jmp |
ALU_ op1 |
ALU_ op2 |
|
Add, Sub |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
|
Load |
0 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
|
Store |
X |
1 |
X |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
|
Sll |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
|
Srl |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
|
Beq |
X |
0 |
X |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
|
Slt |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
|
And , or, not, xor |
1 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
0 |
|
Blt |
X |
0 |
X |
0 |
0 |
0 |
1 |
0 |
0 |
1 |
|
Addi |
0 |
1 |
0 |
1 |
0 |
0 |
0 |
0 |
1 |
1 |
|
Jump |
X |
X |
X |
X |
X |
X |
X |
1 |
X |
x |
|
Nop |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
ALU control inputs:
|
ALUOp1 |
ALUOp0 |
F2 |
F1 |
F0 |
Operation |
|
0 |
0 |
X |
X |
X |
0010 |
|
0 |
0 |
X |
X |
X |
0010 |
|
0 |
1 |
X |
X |
X |
0110 |
|
1 |
0 |
0 |
0 |
1 |
0010 |
|
1 |
0 |
1 |
1 |
0 |
0110 |
|
1 |
0 |
0 |
1 |
0 |
0000 |
|
1 |
0 |
0 |
1 |
1 |
0001 |
|
1 |
0 |
1 |
0 |
1 |
0111 |
November 17:
· All code objects have been defined- That is, everything is represented as objects (ALU, Register, ... ect)
· Currently working on flow
Part of code shown below:
int
main(int argc, char
{
InstructionFetchStage IF_S;
InstructionDecodeStage ID_S;
ExecuteStage EX_S;
//begin execution
while(true)
{
//Instructin Fetch Stage
IF_S.IF_ID.instruction=IF_S.mem.getMemData(IF_S.pc.getPC());
IF_S.IF_ID.adderOut=IF_S.adder.Add16((short)IF_S.pc.getPC(),4);
//Instruction Fetch Stage ends
//Insruction Decode Begins
ID_S.ID_EX.ctrl.setControlLines(IF_S.IF_ID.getOpcode());
ID_S.ID_EX.reg1dat= ID_S.regs.GetRegContent(IF_S.IF_ID.getRS());
ID_S.ID_EX.reg2dat= ID_S.regs.GetRegContent(IF_S.IF_ID.getRT());
ID_S.ID_EX.imediateExteded= ID_S.ext.extend(IF_S.IF_ID.getImidiate());
ID_S.ID_EX.rtreg= IF_S.IF_ID.getRT();
ID_S.ID_EX.rdreg= IF_S.IF_ID.getRD();
//fetch the next instruction :D
IF_S.IF_ID.instruction=IF_S.mem.getMemData(IF_S.pc.getPC());
IF_S.IF_ID.adderOut=IF_S.adder.Add16((short)IF_S.pc.getPC(),4);
//end Instruction fetch stage
}
return 0;
}
Final Report:
http://docs.google.com/Doc?docid=0AaH_h-JGAl1sZGQzc3d3bnNfOTFnN2t4dzRkag&hl=en
Final Deliverable:
http://www.ece.msstate.edu/~rao28
