From Ece

Proposal Team SesserStill

Team Members

Jim Sesser*

Kevin Still

Jeremy Lewis

*Team Leader

Design Overview

The CPU will be designed to use the rising edge of the clock to cycle. There will 8 16 bit registers along with 128 (8 by 16) bytes of memory for storage. Fifteen instructions will be implemented. Shifting will be used for multiplication and division. This will be simulated using Java.

Instruction format

R-Format

OpCode	RS	RT	RD	Func
5 bits	3 bits	3 bits	3 bits	2 bits

I-Format

OpCode	RS	RD	Immediate
5 bits	3 bits	3 bits	5 bits

J-Format

OpCode	Address
5 bits	11 bits

Instructions

Name	Mnemonic	Operation	Opcode	Func	Format
Add Immediate	addi	addi $s1,$s2, 100; $s1=$s2+100	01000	00	I
Sub Immediate	subi	subi $s1,$s2, 100; $s1=$s2-100	01001	00	I
Exclusive OR Immediate	xori	xori $s1,$s2, 100; $s1=$s2 xor 100	01010	00	I
And Immediate	andi	andi $s1,$s2, 100; $s1=$s2&100	01011	00	I
Set Less Than Immediate	slti	slti $t1,$t0, 0x0100, $t=$t0<0x0100	01100	00	I
Addition	add	add $s1,$s2, $s3; $s1=$s2+$s3	11001	00	R
Subtraction	sub	sub $s1,$s2, $s3; $s1=$s2-$s3	11010	00	R
Exclusive OR	xor	xor$s1,$s2, $s3; $s1=$s2 xor $s3	11011	00	R
OR	or	or $v1, $v1, $v0; $v1=$v1\|\| $v0	11100	00	R
Nand	nand	nand $a0, $a0, $a2; $a0=$a0 !& $a2	11101	00	R
Shift Right Logical	srl	srl $t0, $v0, 3; $v0=$v0 / 8	11110	00	R
Shift Left Logical	sll	sll $v2, $v2, 2; $v2=$v2 * 4	11111	00	R
Branch Equal	be	be $t0,$zero EndWhile:	10001	00	I
Load Word	lw	lw $t1, 16($a0); $t1=$a0[16]	10010	00	I
Store Word	sw	sw $t1, 16($a0); $a016=$t1	10100	00	J
Jump	j		10011	00	J

Assembly language and machine code for the test program (Pseudocode)

Pseudocode

 while ($a1 > 0) do { 
   $a1 = $a1 –1; 
   $t0 = Mem[$a0]; 
   if ($t0 > 0100hex) 
   then {
       $v0 = $v0 ÷ 8; 
       $v1 = $v1 | $v0;     //or Mem[$a0] = FF00hex;
   } else {
       $v2 = $v2 × 4; 
       $v3 = $v3 ⊕ $v2;     //xor Mem[$a0] = 00FFhex;
   } 
   $a0 = $a0 + 2;}

Registers

v0	000 //Binary Designator
v1	001 //Binary Designator
v2	010 //Binary Designator
v3	011 //Binary Designator
t0	100 //Binary Designator
t1	101 //Binary Designator
a0	110 //Binary Designator
a1	111 //Binary Designator

Assembly

Assembly Language	Machine Code
StartWhile:
slti $t0, $zero, $a0	0110010011100000
be $t0,$zero EndWhile:	1000110000001101
subi $a1, $a1, 1	0100111111100001
lw $t1, 8($a0)	1001010111000000
slti $t1,$t0, 0x0100	0110010110000100
be $t1, 1 ELSE	1000110100101001
srl $t0, $v0, 3 (to divide by 8)	1111010010000011
or $v1, $v1, $v0	1110000100100000
j endElse	1001100000001011
ElSE:
sll $v2, $v2, 2 (to multiply by 4)	1111101001000010
xor $v3, $v3, $v2	1101101101101000
endElse
addi $a0, $a0, 2	0100011011000010
j StartWhile	1001100000000000
EndWhile

Tasks and Schedule

Name	November 3rd	November 10th	November 19th
Jim Sesser	Get website up and check ability to access	Instruction setup	Final Report Writeup
Kevin Still	Get website up and check ability to access	Memory Setup	Error checking and finalizing
Jeremy Lewis

Planned Meetings

The design team will meet biweekly on Tuesday and Thursday. Document collaboration will be through Google Docs/wave.

Attendance

Date	Attendance	Method
10/26/09	Sesser, Still	gDocs/Chat
10/29/09	Sesser, Still	Chat/wiki
11/3/09	Sesser, Still	Chat/wiki
11/19/09	All	Face to Face

Team Name

The team name is the very original "SesserStill."

Contribution Report

Stage	Task	Name	Contributions(hr)
Proposal	Discussion	Sesser, Still	1 each
	Design Instruction	Sesser, Still	1 each
	Writing Proposal	Sesser, Still	1 each
Web Page	Discussion	Sesser, Still	1.5 each
Web Page	Implementation	Sesser, Still	1 Sesser; 3.5 Still
Coding	Memory	Still	10hr
	Functions	Still	25
	Testing	Still	10
Final Report	Initial setup	Sesser	45 min
	Creation	Still, Lewis	1 hr
	Finalization	Still	30 min
Demonstration	*	*	*
	*	*	*
	*	*	*

Jim Sesser	Signature:	_________________________
Kevin Still	Signature:	_Kevin Still________
Jeremy Lewis	Signature:	_________________________

Deliverables

Proposal

Personal tools

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