ECE4743 Digital Systems Design

From Ece

Revision as of 15:48, 4 November 2009

Syllabus

Syllabus and Class Policy

Class Time & Location

MWF 10:00-10:50am

Simrall 213

Instructor

Thomas Morris

Assistant Professor

Office hours: Monday 4-5pm., Friday 4-5pm.

Lab

Instructor: Clint Howell email: cdh92@ece.msstate.edu

Textbook

HDL (2nd Edition), Samir Palnitkar, Prentice Hall, ISBN 0130449113

This book is recommended for students who plan to pursue digital design as a career or who desire more information on the Verilog HDL. This book is not required.

Class e-mail

ece4743@ece.msstate.edu

Grade Determination

Grading Scheme

Prerequisites

Digital Devices (ECE3714)

• Topics
• Sample exercises

Lecture Slides

1. Class Introduction
2. Basic Logic Part 1
3. Basic Logic Part 2
4. Basic Logic Verilog Examples
5. Verilog for Combinatorial Logic
6. Sequential Logic
7. Verilog for Sequential Logic
8. Shift-Add-3 Algorithm
9. Validation Tips
10. FSM Review
11. Verilog FSM: 2 Process vs. 3 Process
12. Verilog FSM Template
13. Verilog Tasks
14. Verilog for Simulation
15. Intro to Datapath Design
16. Datapath Design Examples
17. Memories
18. System Timing
19. Exam 2 Review
20. Pipe Lines

Project

1. Project Description
2. RTL Handoff
3. Mouse Movement Rubric
4. Extra Credit

Homework

1. Homework #1
2. Homework #2
3. Homework #3
4. Homework #4
5. Homework #5

1. Homework #1 Solutions
2. Homework #2 Solutions
3. Homework #3 Solutions
4. Homework #4 Solutions
5. Homework #5 Solutions

Tests

1. Test 1 Key
2. Test 2 Undergraduate Key
3. Test 2 Graduate Key

Old Tests

1. Fall 2008 Test #1
2. Fall 2008 Test #1 Solutions
3. Fall 2008 Test #2
4. Fall 2008 Test #2 Solutions
5. Fall 2008 Test #3
6. Fall 2008 Test #3 Solutions
7. Spr 2009 Test #1
8. Spr 2009 Test #1 Solutions
9. Spr 2009 Test #2
10. Spr 2009 Test #2 Solutions

Old Homework

1. Homework #1
2. Homework #1 Solutions
3. Homework #2
4. Homework #2 Solutions
5. Homework #3
6. Homework #3 Solutions
7. Homework #4
8. Homework #4 Solutions
9. Homework #5
10. Homework #5 Solutions
11. Homework #6
12. Homework #6 Solutions

Software

We will be using a software package called Xilinx ISE WebPack for digital logic programming in this class. This is free software that can be downloaded from the Xilinx web page. For simulations, we will use the Modelsim software, which is also a free download from the Xilinx web page. We will discuss how to install and use the software in lab. The labs will be oriented around your laptops, so you will need to install the software yourself. You must have the software downloaded before coming to lab since it is a very large download (~850MB). Instructions for downloading it are included in lab 1. This software is also available on the workstations in the lab if you do not have a laptop. You can also use the Quick Start Tutorial to answer many questions about how to use the software, including HDL and schematic entry, simulation, constraints, implementing, and downloading.

Xilinx ISE WebPack Download

Please be sure to download version 9.2i. You will need to register first then return to the above link to download the correct version.

Hardware

The labs this semester will require each student to purchase the Digilent, Inc. Basys development board. These cost $57 each and can be purchased directly from the Digilent, Inc. homepage (see below how to get the $57 price). Included with each kit is a power supply and download cable. We decided to do this so each student can have hands-on experience with FPGA hardware. Each board has 8 LEDs, 8 switches, 4 push buttons, and a 4 digit numerical display. There are also connections for a VGA monitor and a PS/2 port for keyboards/mice. We will be using all of these in the lab.

1. Basys reference manual
2. Basys board schematic

We strongly recommend doing the labs on your laptops. If your laptops do not have a parallel port, then you won't be able to use the download cable. If you don't have a suitable laptop, some computers will be available in lab for development and programming.

To order the Basys development board enter "MSU4743" in the "enter value code" box on the Digilent, Inc. homepage. This should pop up a page which says among other things "Mississippi State University". Next add to cart and check out.

Labs

1. Lab 1
2. Lab 2
3. Lab 3
4. Lab 4
5. Lab 5
6. Lab 6
7. Lab 7

Lab Tips

• Make sure you are using Device = "XC3S100E", Package = "TQ144".
• General:
  • Be sure to include the constraints file in your project. If you're seeing strange things on the outputs, this may be the problem.
  • If your code compiles, but doesn't do what you want it to: READ THE WARNINGS
    • The warnings are there to tell you that you probably made a mistake, but it will compile your code anyway
    • If it optimized something out, it will give you a warning - that's usually a mistake
    • It will tell you when it finds an asynchronous loop
    • It will tell you of unassigned I/O
• Verilog code:
  • Make simple always blocks
    • Only assign few related outputs
    • More smaller process statements are better than one big one
    • The compiler is not very smart
  • Always be able to draw a block diagram of the circuit you are trying to describe
  • Watch out for asynchronous loops in your code
    • Make sure you can't trace a combinatorial path
    • Temporary signals make this deceptive
• Schematic Entry:
  • Use the wire naming tool - don't double click on a wire to name it
  • If you rename a wire, it will rename all of the wires of the same name

Reference Material

• Verilog
  • Verilog HDL Quick Reference Guide
  • Introduction to Verilog
  • Verilog.org
  • An Introduction to the Concepts of Timing and Delays in Verilog
• Other Universities using FPGAs
  • Oregon Institute of Technology
  • University of California, Santa Cruz
  • Worcester Polytechnic Institute
  • LaFayette College

Academic support

In compliance with and in the spirit of the Americans with Disabilities Act (ADA), academic accommodations are made for any student with a documented disability. Students should register with the Office of Student Support Services in Montgomery Hall at (662) 325-3335 as soon as possible to better ensure such accommodations are implemented in a timely fashion and comply with their policies. Any student who believes they may need accommodations in this class are encouraged to contact Student Support Services If Student Support Services has a prescribed course of action for you with regard to this class, please visit me during office hours so we can make the proper arrangements.

Academic Integrity

Mississippi State University has an approved Honor Code that applies to all students. The code is as follows:

"As a Mississippi State University student I will conduct myself with honor and integrity at all times. I will not lie, cheat, or steal, nor will I accept the actions of those who do."

Upon accepting admission to Mississippi State University, a student immediately assumes a commitment to uphold the Honor Code, to accept responsibility for learning, and to follow the philosophy and rules of the Honor Code. Students will be required to state their commitment on examinations, research papers, and other academic work. Ignorance of the rules does not exclude any member of the MSU community from the requirements or the processes of the Honor Code. For additional information please visit: http://www.msstate.edu/dept/audit/1207A.html