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Team - Ece
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Team

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Revision as of 02:39, 6 November 2009

#ONE Project Proposal


Contents

  • 1 Team Name and Members
  • 2 Design Overview
  • 3 Instruction format
  • 4 Instructions and Opcodes
  • 5 Assembly language and machine code for the test program (Pseudocode)
  • 6 Tasks and Schedule
  • 7 Planned Meetings

Team Name and Members

Team name: #One

Team member: Joseph Lee Burnham, Justin Geeslin, Euntai Jung


Design Overview

Our given instruction set was determined from the pseudo code that was provided to us in the project guide. We broke down the pseudo code and determined which instructions would be needed to perform all of the tasks that were specified. We determined that the 18 instructions in our set would be enough to satisfy all of the conditions provided by the code as well as handle any others that might eventually come up.

We decided on four types of instructions I-type instructions, R-type instructions, J-type instructions, and S-type instructions. The R, I, and J type instructions are all the same as the ones that were discussed in class. The S type instructions in a instruction type that was defined by us. We decided to create it because of the constraints in using 16 bit pathways. We found that using regular I type commands we could not take in an immediate value larger than 6 bits but we had to be able to deal with values up to 256 which is 9 bits. Thus we changed the instruction to overwrite the register that was input with the immediate in the case of S type commands. 

Our clock will be set to load data on the rising edge of our clock. On the falling edge we will store data. This applies to both registers and data memory. All other major blocks will not have a preference to rising or falling edge at this time.


Instruction format

R-type:

OpCode [15:12]

Rs [11:9]

Rt [8:6]

Rd [5:3]

Function [2:0]

I-Type:

OpCode [15:12]

Rs [11:9]

Rt [8:6]

Immediate [5:0]

S-type (Set) :

OpCode [15:12]

Rs/Rt [11:9]

Immediate [8:0]

J-type:

OpCode [15:12]

Immediate [11:0]


Instructions and Opcodes

R-type:

Decimal number

Opcode

Command

Function

0

0000

add

000

0

0000

sub

001

0

0000

or

010

0

0000

xor

011

0

0000

and

100

I-type:

Decimal number

Opcode

Command

1

0001

sll

2

0010

srl

3

0011

ori

4

0100

slti

7

0111

addi

12

1100

subi

5

0101

beq

6

0110

bne

8

1000

lw

9

1001

sw

S-type:

Decimal number

Opcode

Command

10

1010

suw

11

1001

slw

J-type:

Decimal number

Opcode

Command

17

1111

j


Assembly language and machine code for the test program (Pseudocode)

Pseudocode for the test program (refer to the project handout):


$v0 = 0040hex; // you can redefine $v0-3, $t0, and $a0-1 with

$v1 = 1010hex; // your register numbers such as $1, $2, etc.

$v2 = 000Fhex;

$v3 = 00F0hex;

$t0 = 0000hex;

$a0 = 0010hex;

$a1 = 0005hex;

while ($a1 > 0) do {

$a1 = $a1 –1;

$t0 = Mem[$a0];

if ($t0 > 0100hex) then {

$v0 = $v0 ÷ 8;

$v1 = $v1 | $v0; //or

Mem[$a0] = FF00hex;

}

else {

$v2 = $v2 × 4;

$v3 = $v3 ⊕ $v2; //xor

Mem[$a0] = 00FFhex;

}

$a0 = $a0 + 2;

}

return;


Assembly Language
Machine Code
$v0 = 0040
Suw $0,#00 1010 000 000000000
Slw $0, #40 1011 000 001000000
$v1 = 1010
Suw $1, #10 1010 001 000010000
Slw $1, #10 1011 001 000010000
$v2 = 000F
Suw $2, #00 1010 010 000000000
Slw $2, #0F 1011 010 000001111
$v3 = 00F0
Suw $3, #00 1010 011 000000000
Slw $3, #F0 1011 011 011110000
$t0 = 0000
Suw $4, #00 1010 100 000000000
Slw $4, #00 1011 100 000000000
$a0 = 0010
Suw $5, #00 1010 101 000000000
Slw $5, #10 1011 101 000010000
$a1 = 0005
Suw $6, #00 1010 110 000000000
Slw $6, #05 1011 110 000000101
While ($a1 > 0) do {
Slti $6, 0 0100 110 000000000
Suw $7, 0 1010 111 000000000
Slw $7, 0 1011 111 000000000
Beq $6, $7, while 0101 110 0111xxxxx //x's for address of while
$a1 = $a1 – 1
Subi $6, 1 1100 110 000000001
$t0 = mem[$a0]
Lw $4, $5, 0 1011 100 101000000
If ($t0 > 0100)
Slti $4, #100 0100 100 1000000000
Suw $7, 0 1010 111 0000000000
Slw $7, 1 1011 111 0000000001
Beq $4, $7, else 0101 100 0111xxxxxx
$v0 = $v0 / 8
Srl $0, 3 0010 000 0000000011
$v1 = $v1 | $v0
Or $1, $1, $0 0000 001 001 000 010
Mem[$a0] = FF00
Suw $7, #ff 1010 111 011111111
Slw $7, #00 1011 111 000000000
Lw $7, $5, 0 1001 111 101000000
$v2 = $v2 x 4
Sll $s2, 2 0001 010 000000010
$v3 = $v3 ⊕ $v2
Xor $3, $3, $2 0000 011 011010011
mem[$a0] = 00FF
Suw $7, #00 1010 111 000000000
Slw $7, #ff 1011 111 011111111
$a0 = $a0 + 2
Addi $5, 2 0111 101 000000010


Tasks and Schedule

Name

Tasks

Week #1

Week #2

Week #3

Week #4

Week #5

Justin Geeslin

Design

Coding

Report

Web Design

 

X

 

 

X

X

 

 

X

X

 

 

 

X

X

 

 

 

X

 

Joseph Lee Burnham

Design

Coding

Report

Web Design

X

X

X

X

X

X

 

 

X

X

 

 

X

X

Euntai Jung

Design

Coding

Report

Web Design

 

 

 

X

 

 

 

X

 

X

 

X

 

X

X

X

 

 

X

X


Planned Meetings

The design team will meet on the following dates to discuss the project progress and assigned tasks:

  • Thursday October 29th 2pm – 3pm
  • Thursday November 5th 2pm – 3pm
  • Thursday November 12th 2pm – 3pm
  • Thursday November 19th 2pm – 3pm
Retrieved from "http://www.ece.msstate.edu/wiki/index.php/Team"
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