Team Zulu:
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Revision as of 06:51, 6 November 2009
Team Zulu is an ECE4713_Computer_Architecture project team that is currently working on implementing a partial CPU based on the MIPS architecture.
Contents |
Team Members
- Jacob Bowen
- Jacob Morgan
- Tim Pitts
Individual Contributions
The table below lists the group members' contribution to different areas of the project.
| Name | Date | Task | Time Spent |
|---|---|---|---|
| Tim | 10/28 | Web Update | 2 hours |
| Tim | 10/31 | Xilinx Project Creation and Initial Coding | .5 hours |
| Jake B. | 11/1 | Hazard Detection Unit (design and testing) | 2 hours |
| Jacob | 11/1 - 11/3 | Downloading and installing Xilinx | 5 hours |
| Jacob | 11/3 | Shift left 2 bits module (design and testing) | 2 hours |
| Jake B. | 11/3 | PC, Sign Extend, and Adder Modules (design and testing) | 1.5 hours |
Team Meetings
The table below lists all team meetings that have been held to date.
| Date(MM/DD/YY) | Time | In Attendance |
|---|---|---|
| 10/27/09 | 2:30 - 3:00 P.M. | All |
Implementation Language and Hardware
Team Zulu has decided to implement the processor on the Basys Development Board using Verilog HDL.
Project Proposal
Design Overview
The instruction set was chosen to be capable of running the test program. Rising edge triggered clocking methodology will be used. Eight registers will be available for the program to use.
Instruction Format
R-Format
| opcode | rs | rt | rd | funct |
| 4 bits | 3 bits | 3 bits | 3 bits | 3 bits |
I-Format
| opcode | rs | rt | immediate |
| 4 bits | 3 bits | 3 bits | 6 bits |
J-Format
| opcode | address |
| 4 bits | 12 bits |
L-Format
| opcode | rs | immediate |
| 4 bits | 3 bits | 9 bits |
Instructions
| Name | Mnemonic | Operation | Opcode | Funct | Format |
|---|---|---|---|---|---|
| Add | add | add $s1,$s2,$s3 | 0000 | 000 | R |
| Subtract | sub | sub $s1,$s2,$s3 | 0000 | 001 | R |
| And | and | and $s1,$s2,$s3 | 0000 | 010 | R |
| Or | or | or $s1,$s2,$s3 | 0000 | 011 | R |
| Nor | nor | nor $s1,$s2,$s3 | 0000 | 100 | R |
| Xor | xor | xor $s1,$s2,$s3 | 0000 | 101 | R |
| Set if less than | slt | slt $s1,$s2,$s3 | 0000 | 110 | R |
| Add immediate | addi | addi $s1,$s2,4 | 0001 | XXX | I |
| Shift left | sll | sll $s1,$s2,4 | 0100 | XXX | I |
| Shift right | srl | srl $s1,$s2,4 | 0101 | XXX | I |
| Load word | lw | lw $s1,4($s2) | 0110 | XXX | I |
| Store word | sw | sw $s1,4($s2) | 0111 | XXX | I |
| Branch if equal | beq | beq $s1,$s2,Dest | 1000 | XXX | I |
| Branch if not equal | bne | bne $s1,$s2,Dest | 1001 | XXX | I |
| Jump | j | j Dest | 1010 | XXX | J |
| Load lower immediate | lli | lli $s1,4 | 1011 | XXX | L |
| Lower upper immediate | lui | lui $s1,4 | 1100 | XXX | L |
Assembly Language and Machine Code for the Test Program (Pseudocode)
$v0 = 0040hex;
$v1 = 1010hex;
$v2 = 000Fhex;
$v3 = 00F0hex;
$t0 = 0000hex;
$a0 = 0010hex;
$a1 = 0005hex;
while($a1 > 0)
{
$a1 = $a1 – 1;
$t0 = Mem[$a0];
if($t0 > 0100hex)
{
$v0 = $v0 ÷ 8;
$v1 = $v1 | $v0;
Mem[$a0] = FF00hex;
}
else
{
$v2 = $v2 × 4;
$v3 = $v3 Å $v2;
Mem[$a0] = 00FFhex;
}
$a0 = $a0 + 2;
}
| Assembly Language | Machine Code |
|---|---|
| while: | |
| slt $t0,$a0,$zero | 0000 110 000 101 110 |
| bne $t0,$zero,end | 1001 101 000 011010 |
| beq $a0,$zero,end | 1000 110 000 011010 |
| addi $a1,$a1,-1 | 0001 111 111 111110 |
| lw $t0, 0($a0) | 0110 110 101 000000 |
| if: | |
| addi $v0,$zero,16 | 0001 001 000 010000 |
| slt $v1,$t0,$v0 | 0000 101 001 010 110 |
| bne $v1,$zero,else | 1001 010 000 001111 |
| beq $t0,$zero,else | 1000 101 000 001111 |
| srl $v0,$v0,3 | 0101 001 001 000011 |
| or $v1,$v1,$v0 | 0000 010 001 010 011 |
| lli $t0,0x100 | 1011 101 100000000 |
| lui $t0,0x7F | 1100 101 001111111 |
| sw $t0,4($a0) | 0111 110 101 000100 |
| j end | 1010 000001100000 |
| else: | |
| sll $v2,$v2,2 | 0100 011 011 000010 |
| nor $t0,$zero,$v3 | 0000 000 100 101 100 |
| nor $v0,$zero,$v2 | 0000 000 011 001 100 |
| or $t0,$t0,$v0 | 0000 101 001 101 011 |
| or $v1,$v3,$v2 | 0000 100 011 010 011 |
| and $v3,$t0,$v1 | 0000 101 010 100 010 |
| lli $t0,0x0FF | 1011 101 011111111 |
| lui $t0,0x00 | 1100 101 000000000 |
| sw $t0,8($a0) | 0111 110 101 001000 |
| endelse: | |
| addi $a0,$a0,2 | 0001 110 110 000010 |
| j while | 1010 000000000000 |
| end: |
Tasks and Schedule
Planned Meetings
- Tuesday, October 27th 4:30 P.M.
- Thursday, October 29th, 4:30 P.M.
- Sunday, November 1st, 6:00 P.M.
- Tuesday, November 3rd, 4:30 P.M.
- Thursday, November 5th, 4:30 P.M.
- Sunday, November 8th, 6:00 P.M.
- Tuesday, November 10th, 4:30 P.M.
- Thursday, November 12th, 4:30 P.M.
- Sunday, November 15th, 6:00 P.M.
- Tuesday, November 17th, 4:30 P.M.
- Thursday, November 19th, 4:30 P.M.
