Robert Reese

Ph.D., Texas A&M University, 1985

Associate Professor, Electrical and Computer Engineering

Research Interests

VLSI CAD Frameworks
Computer Architecture
High-Level System Synthesis
VHDL Modeling
Asynchronous Design

Educational Projects

Zigbee-subset/802.15.4 Multi-platform Protocol Stack

Courses (Current Semester)

Courses (old)

Contact Information

Email: reese@ece.msstate.edu
Office Phone: (662) 325-3154
Fax: (662) 325-2298

(EE/COEN Department)
P.O. Box 9571
Mississippi State, MS 39762

FedX:
216 Simrall, Hardy Road
Starkville, MS 39759

Publications

Books

R. Reese, J. W. Bruce, Bryan A. Jones, Microcontrollers: From Assembly to C Using the PIC24 Family, ISBN: 1-58450-584-4, Delmar Cengage, December 2008, 838 pp. The book supplemental website is www.reesemicro.com .
R. Reese, Microprocessors: From Assembly to C Using the PIC18xx2, ISBN: 1-58450-378-5, Delmar Cengage, July 2005, 664 pp. The book supplemental website is www.reesemicro.com .

EBooks

Robert B. Reese, Mitchell A. Thornton, "Introduction to Logic Synthesis using Verilog HDL" , Synthesis Lectures on Digital Circuits and Systems, ISBN-10:1598291068 (paperback), ISBN-10:1598291076,(doi:10.2200/S00060ED1V01Y200610DCS006) (ebook), Morgan & Claypool, 2006, 84 pp.
Justin Davis, Robert Reese, "Finite State Machine Datapath Design, Optimization, and Implementation", Synthesis Lectures on Digital Circuits and Systems, Morgan & Claypool,2007, Vol. 2,No. 1, 113 pg. (doi: 10.2200/S00087ED1V01Y200702DCS014).

Book Chapters

Reese, R., "Chapter 10.2.1: VHDL Synthesis", Microsystems Technology for Multimedia Applications - An Introduction, ed: Bing Sheu et al, IEEE Press 1995, pp 675-684.
Reese, R., "Schematic Entry", Anatomy of a Silicon Compiler, Robert W. Brodersen, ed., Kluwer Academic Publishers, 1992.
Reese, R., and Barry Boes, "Standard Cell Design", Anatomy of a Silicon Compiler, Robert W. Brodersen, ed., Kluwer Academic Publishers, 1992.
Reese, R., "Appendix B: Training and Distribution", Anatomy of a Silicon Compiler, Robert W. Brodersen, ed., Kluwer Academic Publishers, 1992.

Journals

C. Wang, N. Srivastava, B. A. Jones, R. B. Reese, "A novel multiple species ringdown spectrometer for in situ measurements of methane, carbon dioxide, and carbon isotope", Applied Physics B, Lasers and Optics, 92,2008,pp 259-270.
R. Reese, M. Thornton, and C. Traver, "A Coarse-Grain Phased Logic CPU", IEEE Transactions on Computers,Vol 54, No. 7, July 2005, pp 788-799. 2005.
R. Reese, M. Thornton, C. Traver, and D. Hemmendinger, "Early Evaluation for Performance Enhancement in Phased Logic", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol.24, No.4, April 2005, pp. 532-550.
Traver, C., Harden, J. C; Reese, R.B.; "Asynchronous rate divider and multiplier for LEDR logic", Electronics Letters, Volume 40, Issue 7, 1 April 2004, Pages: 414-415.
R. Reese, M. Thornton and C. Traver, "Two-phase micropipeline control wrapper with early evaluation" Electronics Letters,Volume: 40 , Issue: 6 ,March 2004, Pages:365 - 366.
J.W. Bruce, J. C. Harden, and R. B. Reese " Cooperative and Progressive Design Experience for Embedded Systems", IEEE Transactions on Education, Volume: 47, Issue: 1, Feb. 2004, Pages:83 - 92.
R. Reese, M. Thornton and C. Traver, "Fast two-phase micropipeline control wrapper for standard cell implementation",Electronics Letters ,Volume: 40 ,Issue: 4 ,Feb 2004,Pages:227 - 229.
Calhoun J.S., V. K. Madisetti, R. B. Reese, T. Egolf., "Developing and Distributing Component-Level VHDL Models", Journal of VLSI Signal Processing, Vol 15 (1996), pp 111-126.

Conferences

R. B. Reese, S. C. Smith, and M. A. Thornton, "Uncle - An RTL Approach to Asynchronous Design," in Asynchronous Circuits and Systems (ASYNC), 2012 18th IEEE International Symposium on, 2012, pp. 65-72.
K.Fazel, M. Thornton, R. Reese, "Early Evaluation for Phased Logic Circuits Using BDDs and MVL", IEEE Pacific Rim Conference on Communications, Computers and Signal Processing (PACRIM), August 24-26, 2005, pp 400-403.
R. Reese, M. Thornton and C. Traver, "A Coarse-grained Phased Logic CPU", Ninth International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2003), Vancouver, BC, Canada, May 2003, pp 2-13.
R. Reese, M. Thornton and C. Traver, "A Fine-grained Phased Logic CPU", IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), Tampa, Florida, February, 2003, pp 70-79.
K. Fazel, M. Thornton and R. Reese, PLFire: A Visualization Tool for Asynchronous Phased Logic Designs, IEEE/ACM Conf. On Design, Automation and Test in Europe (DATE), March 2003, pp 1096-1097.
Sakkina B. Sikandar-Gani and R. B. Reese, "Control versus Compute Power within a LEDR-style Self-timed Multiplier with Bypass Path", presented at 45th IEEE MWSCAS Conference, August 4-7, 2002, Tulsa, OK.
M. Thornton, K. Fazel, R. B. Reese, C. Traver, "Generalized Early Evaluation in Self-timed Circuits", Proceedings of the Design, Automation and Test in Europe Conference, Paris, France, March, 2002, pp 255-259.
R. Reese, C. Traver, and M. Thornton, "Arithmetic Logic Circuits using Self-timed Bit Level Dataflow and Early Evaluation", Proceedings of the International Conference on Computer Design, Austin, TX, September, 2001, pp 18-23.
C. Traver, R. B. Reese, M. A. Thornton, "Cell Designs for Self-timed FPGAs", Proceedings of the 2001 ASIC/SOC Conference, September 2001, pp 175-179.
H. Lavana, F. Brglez, R. Reese, G. Konduri., A. Chandrakasan," OpenDesign: an open user-configurable project environment for collaborative design and execution on the Internet", Proceedings of the 2000 International Conference on Computer Design, 2000, 17-20 Sept. 2000, pp. 567 - 570.
Hemang Lavana, Franc Brglez, Robert Reese, "User-Configurable Experimental Design flows on the Web: The ISCAS'99 Experiments", IEEE Proceedings of the Intl Symposium on Circuits and Systems (ISCAS '99), Orlando, FL, May 30, 1999, pp. 440-443.
Reese, R., D. Brown,"VHDL Modeling and Tutoring Efforts by Mississippi State University ", Rapid Systems Prototyping with VHDL, Proceedings of VHDL International Users Forum, October 20-22, 1997, Arlington, VA, pp179-182.
Reese, R., C. McCloslkey, V. Sanders, "Redesign of a Generic VHDL Model Template for SRAMs ", Rapid Systems Prototyping with VHDL, , Proceedings of VHDL International Users Forum, October 20-22, 1997, Arlington, VA, pp122-125.
Reese, R., "EDA on Unix/Sparc and Win95/Intel platforms: does compatibility exist?", Proceedings of the1997 IEEE International Conference on Microelectronic Systems Education, 1997, 21-23 July 1997, pp. 32 - 33.
Reese, R., Vince Sanders, "A VHDL Modeling Approach to the Xilinx 4000 Series FPGA", VHDL International User's Forum, October 27-30, 1996, Durham, NC.
Reese, R., J. Scott Calhoun, "Mississippi State Develops on-line FPGA Model Generator", RASSP Digest, Vol 3., September 1996, pp 39-41.
Reese, B., "Using HYPER to teach datapath design techniques in an ASIC design course", Proceedings of Seventh Annual IEEE International ASIC Conference and Exhibit, 1994, 19-23 Sept. 1994, pp. 200 - 203.
R. Reese, C. A. Traver and R. J. Auletta,"On Asynchronous and Synchronous ASIC Standard-Cells,"Canadian Conference on VLSI, Banff, Canada, 1993.
Auletta, R., Reese, B., Traver, C., "A comparison of synchronous and asynchronous FSMD designs", Proceedings of the 1993 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1993. ICCD '93., 3-6 Oct. 1993, pp178 - 182.
Reese, R., "Use of VHDL Synthesis in an Advanced Digital Design Course", Fifth Annual IEEE International ASIC Conference & Exhibit, Rochester, N. Y., Sept 21-25, 1992, pp 263-266.
Reese, R.,"Use of VHDL Synthesis in an Advanced Digital Design Course", IEEE Southeastcon '92, Birmingham, AL, April 1992, pp 509-512.
Reese, R., and J. Harden, "Efficient use of a Behavioral Simulator in an Introductory Computer Architecture Course, Proceedings of the 1991 Microelectronic System Education Conference & Exposition, San Jose, CA, June 23-26, 1991.
Reese, R., "Two TinyChip Projects for an Introductory CAD course," Proceedings of the 1991 Microelectronic System Education Conference & Exposition, San Jose, CA, June 23-26, 1991.

Technical Reports

Reese, R., "UNCLE (Unified NULL Convention Logic Environment)", TR MSU-ECE-10-001, November 2010.

Awards

2007 John Grisham Master Teacher Award, awarded by Mississippi State University.
2006-2007 Outstanding Educator Award, ECE department, as voted on by the students of the ECE department.
2006 Outstanding Research Paper Award, MSU Bagley College of Engineering, for "Early Evaluation for Performance Enhancement in Phased Logic", IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, Vol.24, No.4, April 2005, pp. 532-550, by R. Reese, M. Thornton, C. Traver, and D. Hemmendinger.
2006 Excellence in Undergraduate Teaching Award, Mississippi State University, awarded by the Mississippi State University Alumni Association.
2005 Outstanding Engineering Educator Award, MSU Bagley College of Engineering
2004 Outstanding Instructional Paper Award, MSU Bagley College of Engineering, for "Cooperative and Progressive Design Experience for Embedded Systems", by J.W. Bruce, J. C. Harden, and R. B. Reese in IEEE Transactions on Education, Volume: 47, Issue: 1, Feb. 2004, Pages:83 - 92.
Thomas Evans Award, Best instructional paper in the Southeastern section of the ASEE for 1991, "Efficient use of a Behavioral Simulator in an Introductory Computer Architecture course", R. Reese and J. Harden.
Outstanding Instructional Paper in the College of Engineering for 1991, "Efficient use of a Behavioral Simulator in an Introductory Computer Architecture course", R. Reese and J. Harden.

Patents

R. Reese, Mitchell A. Thornton, "Method for Early Evaluation in Micropipeline Processors", Patent No. US 7,043,710, May 9, 2006.

Hobbies

Anime (faculty advisor to the MSU Anime Club)
Running
Badminton
Paintball , no longer active in this, but some good memories.