Hints on Meeting Project Constraints
Clock Cycle Constraint (12 clocks)
- More resources (multipliers, adders), less clocks
- Can be done with four parallel datapath approach (4 mults + 4 adders)
Clock Frequency Constraint (25 Mhz )
- Will need to pipeline multiplier 1-3 stages
- May need to put DFFs on some control outputs of the FSM
- For state encoding, Gray Code or One Hot encoding will produce faster FSM than Binary Counting order encoding.