Phased Logic Animations ( for more info see Phased Logic Home Page)



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  1. Token flow in small netlist . The green net is a feedback wire that had to be added to ensure safety and liveness in the new netlist. The old netlist had 2 DFFs and 2 Combinational gates.

  2. Seven computation waves through a ripple structure with 1 input stage, 1 output stage. This illustrates bit-level dataflow in a PL system. PL systems only have to be word synchronized at the input/output boundaries -- within PL systems data flows at a bit or nybble level. Average throughput is 4 gate delays.
  3. Seven computation waves through a ripple structure with multiple input/output stages. Notice that input/output stages bracketing the ripple structure can improve throughput. Average throughput has been improved to 2.3 gate delays.
  4. Six computation waves through a netlist. The average throughput of this system is (6+2)/2 = 4 gate delays.
  5. Six computation waves through the same netlist with one extra gate added to shortest delay path. The average throughput of this system is (4+2+2)/3 = 2.7 gate delays. Bit-level data flow takes advantage of whatever parallelism is available.